MC100EP14DT ON Semiconductor, MC100EP14DT Datasheet

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MC100EP14DT

Manufacturer Part Number
MC100EP14DT
Description
IC DRIVER CLOCK ECL 1-5 20TSSOP
Manufacturer
ON Semiconductor
Series
100EPr
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of MC100EP14DT

Number Of Circuits
1
Ratio - Input:output
2:5
Differential - Input:output
Yes/Yes
Input
ECL, HSTL, PECL
Output
ECL, PECL
Frequency - Max
2GHz
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
2GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
MC100EP14DTOS

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MC100EP14
3.3V / 5V 1:5 Differential
ECL/PECL/HSTL Clock Driver
Description
clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single−ended (if the V
the LVEP14 is operating under PECL conditions.
design, layout, and processing minimize skew within a device and from
device to device.
any differential output need to be terminated even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
this device only. For single−ended input conditions, the unused
differential input is connected to V
V
and V
to 0.5 mA. When not used, V
Features
© Semiconductor Components Industries, LLC, 2010
June, 2010 − Rev. 6
BB
The MC100EP14 is a low skew 1−to−5 differential driver, designed with
The EP14 specifically guarantees low output−to−output skew. Optimal
To ensure that the tight skew specification is realized, both sides of
The common enable (EN) is synchronous, outputs are enabled/
The VBB pin, an internally generated voltage supply, is available to
V
V
400 ps Typical Propagation Delay
100 ps Device−to−Device Skew
25 ps Within Device Skew
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode:
NECL Mode:
Open Input Default State
These are Pb−Free Devices
CC
CC
may also rebias AC coupled inputs. When used, decouple V
CC
= 3.0 V to 5.5 V with V
= 0 V with V
via a 0.01 mF capacitor and limit current sourcing or sinking
EE
BB
= −3.0 V to −5.5 V
output is used). HSTL inputs can be used when
BB
EE
should be left open.
BB
= 0 V
as a switching reference voltage.
1
BB
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional marking information, refer to
Application Note AND8002/D.
(Note: Microdot may be in either location)
ORDERING INFORMATION
A
L
Y
W
G
MARKING DIAGRAM*
http://onsemi.com
20
1
CASE 948E
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
DT SUFFIX
TSSOP−20
ALYWG
EP14
Publication Order Number:
100
G
MC100EP14/D

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MC100EP14DT Summary of contents

Page 1

MC100EP14 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100EP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential ...

Page 2

WARNING: All V Figure 1. TSSOP−20 (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Pin Function CLK0*, CLK0** ECL/PECL/HSTL CLK Input CLK1*, CLK1** ECL/PECL/HSTL CLK Input Q0:4, Q0:4 ECL/PECL ...

Page 3

Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...

Page 4

Table 5. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 5

Table 7. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 6

... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP14DT MC100EP14DTG MC100EP14DTR2 MC100EP14DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. 5.0 V 3.3 V É ...

Page 7

Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

Page 8

... −V− 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE Í Í Í Í ...

Page 9

... Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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