MC100LVEP210MNG ON Semiconductor, MC100LVEP210MNG Datasheet

MC100LVEP210MNG

Manufacturer Part Number

MC100LVEP210MNG

Description

IC CLOCK DVR DUAL DIFF 32-QFN

Manufacturer

ON Semiconductor

Series

100LVEPr

Type

Fanout Buffer (Distribution)r

Datasheet

1.MC100LVEP210MNRG.pdf (9 pages)

Specifications of MC100LVEP210MNG

Number Of Circuits

Ratio - Input:output

1:5

Differential - Input:output

Yes/Yes

Input

ECL, HSTL, PECL

Output

ECL, PECL

Frequency - Max

3GHz

Voltage - Supply

2.375 V ~ 3.8 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

32-TFQFN Exposed Pad

Frequency-max

3GHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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MC100LVEP210

2.5V / 3.3V 1:5 Dual

Differential ECL/PECL/HSTL

Clock Driver

Description

designed with clock distribution in mind. The ECL/PECL input

signals can be either differential or single-ended if the V

used. The signal is fanned out to 5 identical differential outputs. HSTL

inputs can be used when the EP210 is operating in PECL mode.

Optimal design, layout, and processing minimize skew within a device

and from device to device.

differential output need to be terminated identically into 50 W even if

only one output is being used. If an output pair is unused, both outputs

may be left open (unterminated) without affecting skew.

operated from a positive V

LVEP210 to be used for high performance clock distribution in +3.3 V

or +2.5 V systems. Single-ended CLK input operation is limited to a

distribute low skew clocks across the backplane or the board. In a

PECL environment, series or Thevenin line terminations are typically

used as they require no additional power supplies. For more

information on using PECL, designers should refer to Application

Note AN1406/D.

Features

•

*For additional information on our Pb-Free strategy and soldering details, please

August, 2007 - Rev. 13

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC100LVEP210 is a low skew 1-to-5 dual differential driver,

The LVEP210 specifically guarantees low output-to-output skew.

To ensure the tight skew specification is realized, both sides of the

The MC100LVEP210, as with most other ECL devices, can be

Designers can take advantage of the LVEP210's performance to

with V

85 ps Typical Device-to- Device Skew

20 ps Typical Output-to-Output Skew

Jitter Less than 1 ps RMS

350 ps Typical Propagation Delay

Maximum Frequency u 3 GHz Typical

The 100 Series Contains Temperature Compensation

PECL and HSTL Mode Operating Range: V

NECL Mode Operating Range: V

Open Input Default State

LVDS Input Compatible

Fully Compatible with MC100EP210

Pb-Free Packages are Available*

≥ 3.0 V in PECL mode, or V

Output

= 0 V

= -2.375 V to -3.8 V

supply in PECL mode. This allows the

≤ -3.0 V in ECL mode.

= 0 V

= 2.375 V to 3.8 V

output is

*For additional marking information, refer to

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

Application Note AND8002/D.

32-LEAD LQFP

CASE 488AM

G or G

(Note: Microdot may be in either location)

CASE 873A

MN SUFFIX

FA SUFFIX

QFN32

ORDERING INFORMATION

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb-Free Package

http://onsemi.com

Publication Order Number:

DIAGRAMS*

AWLYYWWG

MC100LVEP210/D

MARKING

AWLYYWWG

LVEP21

MC100

LVEP210

MC100

Related parts for MC100LVEP210MNG

MC100LVEP210MNG Summary of contents

Page 1

... Fully Compatible with MC100EP210 • Pb-Free Packages are Available* *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2007 August, 2007 - Rev. 13 output is BB ≤ ...

Page 2

V Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 CLKa CLKa MC100LVEP210 V BB CLKb CLKb Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 V CC Warning: All V and V pins must be externally connected ...

Page 3

Table 2. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pull-up Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. ...

Page 4

Table 4. PECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage Common Mode IHCMR Range (Differential Configuration) (Note 4) V Input ...

Page 5

Table 6. NECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 10 Output LOW Voltage (Note 10 Input HIGH Voltage (Single-Ended Input LOW Voltage (Single-Ended Output ...

Page 6

Table 8. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency (Figure 4) maxPECL/ HSTL t Propagation Delay PLH t Propagation Delay @ 2.5 V PHL t Within-Device Skew (Note 14) skew Device-to-Device Skew (Note 15) t CLOCK Random Jitter (RMS) ...

Page 7

... Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVEP210FA MC100LVEP210FAG MC100LVEP210FAR2 MC100LVEP210FARG MC100LVEP210MNG MC100LVEP210MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 8

- DETAIL - -AB- SEATING -AC- PLANE 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ...

Page 9

... X 0.28 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center ...

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