PCK946BD,151 NXP Semiconductors, PCK946BD,151 Datasheet - Page 5

IC DRVR CLK CMOS 1:10 32LQFP

PCK946BD,151

Manufacturer Part Number
PCK946BD,151
Description
IC DRVR CLK CMOS 1:10 32LQFP
Manufacturer
NXP Semiconductors
Type
Fanout Buffer (Distribution), Divider, Multiplexerr
Datasheet

Specifications of PCK946BD,151

Number Of Circuits
1
Ratio - Input:output
2:10
Differential - Input:output
No/No
Input
LVCMOS, LVTTL
Output
CMOS
Frequency - Max
150MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
150MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935281249151
PCK946BD-S
PCK946BD-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCK946BD,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
8. Static characteristics
Table 7:
T
[1]
[2]
9. Dynamic characteristics
Table 8:
[1]
[2]
[3]
9397 750 12296
Product data sheet
Symbol
V
V
V
V
I
C
C
I
Symbol
f
t
t
t
t
t
t
t
t
t
t
I
q(max)
max
PLH
PHL
sk(o)
sk(pr)
PZL
PZH
PLZ
PHZ
r
f
amb
IH
IL
OH
OL
i
PD
The PCK946 can drive 50
line to the termination voltage of V
I
Driving 50
Termination is 50
Part-to-part skew at a given temperature and voltage.
I
= 0 C to +70 C; V
current is a result of internal pull-up/pull-down resistors.
Parameter
maximum input clock frequency
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
output skew time
process skew time
OFF-state to LOW propagation delay
OFF-state to HIGH propagation delay
LOW to OFF-state propagation delay
HIGH to OFF-state propagation delay
rise time
fall time
Static characteristics
Dynamic characteristics
Parameter
HIGH-state input voltage
LOW-state input voltage
HIGH-state output voltage
LOW-state output voltage
input current
input capacitance
power dissipation capacitance
maximum quiescent supply current
transmission lines.
to 0.5V
CC
= 3.3 V
CC
transmission lines on the incident edge. Each output can drive one 50
.
T
= 0.5V
0.3 V
CC
. Alternately, the device drives up to two 50
Rev. 01 — 13 December 2005
Conditions
TCLK to Qn
TCLK to Qn
output-to-output
part-to-part
output; 0.8 V to 2.0 V
output; 2.0 V to 0.8 V
f
same frequency outputs
f
different frequency outputs
f
same frequency outputs
f
different frequency outputs
max
max
max
max
< 100 MHz;
< 100 MHz;
> 100 MHz;
> 100 MHz;
Conditions
I
I
per output
OH
OL
= 20 mA
= 20 mA
Low voltage 1 : 10 CMOS clock driver
[1]
[1]
[2]
Min
2.0
-
2.5
-
-
-
-
-
[1] [2]
[1] [2]
[1] [2]
series terminated transmission lines.
[1]
[3]
[2]
[2]
[2]
[2]
[2]
[2]
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Min
150
4.5
4.5
-
-
-
-
-
-
-
-
-
0.1
0.1
parallel terminated transmission
Typ
-
-
-
-
-
-
25
1
Typ
-
7.5
7.5
-
-
-
-
2.0
3
3
3
3
0.5
0.5
PCK946
Max
3.6
0.8
-
0.4
4
-
2
120
Max
-
11.5
11.5
350
350
350
450
4.5
11
11
11
11
1.0
1.0
Unit
V
V
V
V
pF
pF
mA
Unit
MHz
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
5 of 13
A

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