ADF4360-4BCPZ Analog Devices Inc, ADF4360-4BCPZ Datasheet

IC INT SYNTH/VCO SEALED 24-LFCSP

ADF4360-4BCPZ

Manufacturer Part Number
ADF4360-4BCPZ
Description
IC INT SYNTH/VCO SEALED 24-LFCSP
Manufacturer
Analog Devices Inc
Type
Fanout Distribution, Integer N Synthesizer (RF)r
Datasheet

Specifications of ADF4360-4BCPZ

Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
1.75GHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-LFCSP
Frequency-max
1.75GHz
Pll Type
Frequency Synthesis
Frequency
1.45GHz
Supply Current
10mA
Supply Voltage Range
3V To 3.6V
Digital Ic Case Style
LFCSP
No. Of Pins
24
Operating Temperature Range
0°C To +150°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4360-4EBZ1 - BOARD EVALUATION FOR ADF4360-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
FEATURES
Output frequency range: 1450 MHz to 1750 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
REF
DATA
CLK
LE
IN
ADF4360-4
N = (BP + A)
PRESCALER
P/P+1
DATA REGISTER
24-BIT
COUNTER
14-BIT R
LOAD
LOAD
FUNCTIONAL BLOCK DIAGRAM
REGISTER
COUNTER
COUNTER
INTEGER
13-BIT B
5-BIT A
AGND
FUNCTION
AV
24-BIT
LATCH
DD
DV
DGND
Figure 1.
DD
DETECT
LOCK
COMPARATOR
Integrated Synthesizer and VCO
PHASE
CE
DIVSEL = 1
DIVSEL = 2
GENERAL DESCRIPTION
The ADF4360-4 is a fully integrated integer-N synthesizer
and voltage-controlled oscillator (VCO). The ADF4360-4 is
designed for a center frequency of 1600 MHz. In addition, a
divide-by-2 option is available, whereby the user gets an RF
output of between 725 MHz and 875 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from
3.0 V to 3.6 V and can be powered down when not in use.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
CPGND
R
MULTIPLEXER
CHARGE
SET
PUMP
CORE
VCO
MUTE
© 2004 Analog Devices, Inc. All rights reserved.
OUTPUT
STAGE
÷2
MUXOUT
V
V
RF
RF
CP
C
C
ADF4360-4
VCO
TUNE
C
N
OUT
OUT
A
B
www.analog.com

Related parts for ADF4360-4BCPZ

ADF4360-4BCPZ Summary of contents

Page 1

... Integrated Synthesizer and VCO GENERAL DESCRIPTION The ADF4360 fully integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-4 is designed for a center frequency of 1600 MHz. In addition, a divide-by-2 option is available, whereby the user gets an RF output of between 725 MHz and 875 MHz ...

Page 2

... ADF4360-4 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 Transistor Count........................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Functional Descriptions.......................... 7 Typical Performance Characteristics ............................................. 8 Circuit Description........................................................................... 9 Reference Input Section............................................................... 9 Prescaler (P/P + 1)........................................................................ 9 A and B Counters ......................................................................... 9 R Counter ...................................................................................... 9 PFD and Charge Pump................................................................ 9 MUXOUT and Lock Detect...................................................... 10 Input Shift Register ...

Page 3

... MHz/V typ 15 kHz typ Into 2.00 VSWR load. −19 dBc typ −37 dBc typ −13/−4 dBm typ Programmable steps. See Table 7. ±3 dB typ For tuned loads, see the Output Matching section. 1.25/2.50 V min/max Rev Page ADF4360-4 = 4.7 kΩ. SET ≤ 2 ≤ 2 ...

Page 4

... REFIN PFD MHz MHz 1600; Loop B kHz. REFIN PFD 13 The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF the synthesizer MHz @ 0 dBm. REFOUT B Version Unit −111 dBc/Hz typ −133 dBc/Hz typ − ...

Page 5

... DB22 DB2 (CONTROL BIT C2) Figure 2. Timing Diagram Rev Page ADF4360 unless otherwise noted. A MIN MAX Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width ...

Page 6

... ADF4360-4 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND VCO VCO DD Digital I/O Voltage to GND Analog I/O Voltage to GND REF to GND IN Operating Temperature Range Maximum Junction Temperature CSP θ Thermal Impedance JA (Paddle Soldered) (Paddle Not Soldered) Lead Temperature, Soldering ...

Page 7

... VCO. CP Rev Page DATA 18 CLK 17 REF 16 IN DGND SET must have the same value must have the same value pin is 0.6 V. The relationship between I CP with a 10 µF capacitor. VCO /2 and a dc equivalent input resistance ADF4360-4 and R is SET ...

Page 8

... ADF4360-4 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 1 –80 –90 2 –100 –110 –120 –130 –140 –150 –160 –170 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 4. Open-Loop VCO Phase Noise –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 –120 – ...

Page 9

... Two bits in the R counter latch, ABP2 and ABP1, control the width of the pulse (see Table 9 DIVIDER HI N DIVIDER R DIVIDER N DIVIDER CP OUTPUT Figure 12. PFD Simplified Schematic and Timing (In Lock) Rev Page ADF4360 13-BIT B COUNTER LOAD PRESCALER P/P+1 LOAD 5-BIT A MODULUS COUNTER CONTROL N DIVIDER Figure 11 ...

Page 10

... ADF4360-4 MUXOUT AND LOCK DETECT The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. The full truth table is shown in Table 7. Figure 13 shows the MUXOUT section in block diagram form. ...

Page 11

... If the outputs are used individually, the optimum output stage consists of a shunt inductor to V Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the mute-till-lock detect (MTLD) bit in the control latch ...

Page 12

... ADF4360-4 LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs determines which latch is programmed. Table 6. Latch Structure PRESCALER CURRENT VALUE SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 ...

Page 13

... CP GAIN CURRENT SETTING 1 CURRENT SETTING OUTPUT THREE-STATE OUTPUT ) DIGITAL LOCK DETECT (ACTIVE HIGH DIVIDER OUTPUT DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND ADF4360-4 CONTROL BITS DB2 DB1 DB0 C2 (0) C1 (0) PC1 CORE POWER LEVEL 5mA 10mA 15mA 20mA DD ...

Page 14

... ADF4360-4 Table 8. N Counter Latch DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DIV2 CPG B13 B12 B11 B10 DIVSEL B13 B12 B11 (FUNCTION LATCH) FASTLOCK ENABLE CP GAIN DIV2 DIVIDE-BY-2 0 FUNDAMENTAL OUTPUT DIVIDE-BY-2 1 DIVSEL DIVIDE-BY-2 SELECT (PRESCALER INPUT) ...

Page 15

... ABP1 R14 R13 R12 R11 R10 R9 R14 ABP1 ANTIBACKLASH PULSE WIDTH 0 3.0ns 1 1.3ns 0 6.0ns 1 3.0ns Rev Page DB9 DB8 DB7 DB6 DB5 DB4 DB3 R13 R12 .......... .......... .......... .......... .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... .......... .......... .......... ADF4360-4 CONTROL BITS DB2 DB1 DB0 R1 C2 (0) C1 (1) DIVIDE RATIO 16380 16381 16382 16383 ...

Page 16

... VCO may not be able to oscillate at the desired frequency, which does not allow the band select logic to choose the correct frequency band, and the ADF4360-4 may not achieve lock. If the recommended interval is inserted, and the N counter latch is programmed, the band select logic can choose the correct frequency band, and the part locks to the correct frequency ...

Page 17

... Hardware Power-Up/Power-Down If the ADF4360-4 is powered down via the hardware (using the CE pin) and powered up again without any change to the N counter register during power-down, the part locks at the cor- rect frequency because it is already in the correct frequency band. The lock time depends on the value of capacitance on the C pin, which is < ...

Page 18

... With (C2, C1) = (0, 0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. Prescaler Value In the ADF4360 family, P2 and P1 in the control latch set the prescaler values. Power-Down DB21 (PD2) and DB20 (PD1) provide programmable power- down modes ...

Page 19

... The overall divide range is defined by ((P × A), where P is the prescaler value. CP Gain DB21 of the N counter latch in the ADF4360 family is the charge pump gain bit. When this is programmed to 1, Current Setting 2 is used. When programmed to 0, Current Setting 1 is used. This bit can also be programmed through DB10 of the control latch ...

Page 20

... The AD8349 accepts LO drive levels from −10 dBm to 0 dBm. The optimum LO power can be software programmed on the ADF4360-4, which allows levels from −13 dBm to −4 dBm from each output. The RF output is designed to drive a 50 Ω load but must be ac- coupled, as shown in Figure 17 ...

Page 21

... FIXED FREQUENCY LO Figure 18 shows the ADF4360-4 used as a fixed frequency LO at 1.6 GHz. The low-pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz. The maximum PFD frequency of the ADF4360 MHz. Because using a larger PFD frequency allows users to use a smaller N, the in-band phase noise is reduced to as low as possible, – ...

Page 22

... The user should connect the printed circuit thermal pad to AGND. This is internally connected to AGND. OUTPUT MATCHING There are a number of ways to match the output of the ADF4360-4 for optimum operation; the most basic is to use a 50 Ω resistor bypass capacitor of 100 pF is con- VCO nected in series, as shown Figure 21 ...

Page 23

... ADF4360-4BCPRL −40°C to +85°C ADF4360-4BCPRL7 −40°C to +85°C 1 ADF4360-4BCPZ −40°C to +85°C 1 ADF4360-4BCPZRL −40°C to +85°C 1 ADF4360-4BCPZRL7 −40°C to +85°C EVAL-ADF4360-4EB1 Pb-free model. 4.00 BSC SQ 0.60 MAX 0.50 BSC TOP 3.75 VIEW BSC SQ 0 ...

Page 24

... ADF4360-4 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04438– ...

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