ADF4360-4BCPZ Analog Devices Inc, ADF4360-4BCPZ Datasheet - Page 16

IC INT SYNTH/VCO SEALED 24-LFCSP

ADF4360-4BCPZ

Manufacturer Part Number
ADF4360-4BCPZ
Description
IC INT SYNTH/VCO SEALED 24-LFCSP
Manufacturer
Analog Devices Inc
Type
Fanout Distribution, Integer N Synthesizer (RF)r
Datasheet

Specifications of ADF4360-4BCPZ

Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
1.75GHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-LFCSP
Frequency-max
1.75GHz
Pll Type
Frequency Synthesis
Frequency
1.45GHz
Supply Current
10mA
Supply Voltage Range
3V To 3.6V
Digital Ic Case Style
LFCSP
No. Of Pins
24
Operating Temperature Range
0°C To +150°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4360-4EBZ1 - BOARD EVALUATION FOR ADF4360-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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ADF4360-4
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-4 after
power-up is:
1.
2.
3.
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AV
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-4 during initial power-up to have settled.
Table 10. C
C
10 µF
440 nF
N
Value
R counter latch
Control latch
N counter latch
N
Capacitance vs. Interval and Phase Noise
Recommended Interval between Control Latch and N Counter Latch
≥ 5 ms
≥ 600 µs
POWER-UP
CLOCK
DATA
LE
DD
, DV
DD
LATCH DATA
R COUNTER
, V
VCO
, and CE pins. On
Figure 16. ADF4360-4 Power-Up Timing
LATCH DATA
Rev. A | Page 16 of 24
CONTROL
During initial power-up, a write to the control latch powers up
the part, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not be able to oscillate at the desired frequency,
which does not allow the band select logic to choose the correct
frequency band, and the ADF4360-4 may not achieve lock. If
the recommended interval is inserted, and the N counter latch
is programmed, the band select logic can choose the correct
frequency band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the C
reduce the close-in noise of the ADF4360-4 VCO. The recom-
mended value of this capacitor is 10 µF. Using this value
requires an interval of ≥ 5 ms between the latching in of the
control latch bits and latching in of the N counter latch bits. If a
shorter delay is required, this capacitor can be reduced. A slight
phase noise penalty is incurred by this change, which is ex-
plained further in Table 10.
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
REQUIRED INTERVAL
N
Open-Loop Phase Noise @ 10 kHz Offset
−87 dBc
−86 dBc
pin (Pin 14). This capacitor is used to
LATCH DATA
N COUNTER

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