IC CLOCK SYNTHESIZER 56-TSSOP

MK2069-04GILF

Manufacturer Part NumberMK2069-04GILF
DescriptionIC CLOCK SYNTHESIZER 56-TSSOP
ManufacturerIDT, Integrated Device Technology Inc
TypeClock Synchronizer
MK2069-04GILF datasheet
 


Specifications of MK2069-04GILF

PllYesInputLVCMOS
OutputLVCMOSNumber Of Circuits1
Ratio - Input:output1:3Differential - Input:outputNo/No
Frequency - Max160MHzDivider/multiplierYes/No
Voltage - Supply3.15 V ~ 3.45 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case56-TSSOP
Frequency-max160MHzNumber Of Elements2
Supply Current30mAPll Input Freq (min)1KHz
Pll Input Freq (max)170MHzOperating Supply Voltage (typ)3.3V
Operating Temp Range-40C to 85CPackage TypeTSSOP
Output Frequency Range0.5 to 160MHzOperating Supply Voltage (min)3.15V
Operating Supply Voltage (max)3.45VOperating Temperature ClassificationIndustrial
Pin Count56Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names800-1783
800-1783-5
800-1783
  
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VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Description
The MK2069-04 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that features a PLL
(Phase-Locked Loop) input reference divider and feedback
divider that have a wide numeric range selectable by the
user. This enables a complex PLL multiplication ratio that
can be used for translation between clock frequency
standards.
The on-chip VCXO produces a stable, low jitter output clock
using a phase detector frequency down to 8 kHz or lower.
This means the MK2069-04 can translate between clock
frequencies that have a low common denominator, such as
the 8 kHz frame clock common with telecom standards. The
MK2069-04 also provides jitter attenuation of the input
clock and can accept a low input frequency as well.
The device is optimized for user configurability by providing
access to all major PLL divider functions. No power-up
programming is needed as configuration is pin selected.
External VCXO loop filter components provide an additional
level of user configurability.
The MK2069-04 includes a lock detector (LD) output that
serves as a clock status monitor. The clear (CLR) input
enables rapid synchronization to the phase of a newly
selected input clock.
Block Diagram
R P V
R V 1 1:0
12
R P V
R V
IC L K
D iv id er
D iv id e r
1 , 8
2 to 4 0 9 7
C L R
IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Features
Input clock frequency <1 kHz to 170 MHz
Output clock frequency of 500 kHz to 160 MHz
Clock translation examples:
Jitter attenuation of input clock provided by VCXO circuit.
Jitter transfer characteristics user configured through
external loop filter component selection.
Low jitter and phase noise generation.
PLL lock status output
PLL Clear function allows seamless synchronizing to an
altered input clock phase
2nd PLL provides frequency translation of VCXO PLL
output (VCLK) to a higher or alternate output frequency
(TCLK).
Device will free-run in the absence of an input clock
based on VCXO frequency.
56-pin TSSOP package
Single 3.3 V power supply
5 V tolerant clock input
Pb (lead) free package
P u lla b le
x ta l
S V 1 :0
2
IS E T
L F
L F R
X 1
X 2
P hase
D etector
S V
V C X O
D iv id e r
1 ,2 ,1 2,1 6
C harge
P um p
F V D iv id er
1 to 4 09 6
V C X O
P L L
L o c k D e te c to r
12
L D C
F V 1 1 :0
1
DATASHEET
MK2069-04
T1 (1.544 MHz) to/from E1 (2.048 MHz)
T3 (44.736 MHz) to/from E3 (34.368 MHz)
OC-3 (155.52 MHz) to/from T1 (1.544 MHz)
CCIR-601 (27 MHz) to/from SMPTE 274M (74.125
MHz)
S T
S T
V C O
D ivid e r
2 , 1 6
F T D iv id e r
2 to 1 6 , e v e n o n ly
T ran s la to r
P L L
L D R
3
F T 2 :0
MK2069-04
V D D
4
V C L K
O E V
T C L K
O E T
R C L K
O E R
L D
O E L
4
G N D
REV J 051310

MK2069-04GILF Summary of contents

  • Page 1

    ... External VCXO loop filter components provide an additional level of user configurability. The MK2069-04 includes a lock detector (LD) output that serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock. ...

  • Page 2

    ... Translator PLL Feedback Divider Selection FT2 FT1 Translator PLL Scaling Divider Selection Table ST ST Divider Ratio VCXO AND SYNTHESIZER Divider Notes Ratio 2 RV Divide Value 3 = Address + 2 : 4097 Notes 2 For FV addresses 0 to 4094, FV Divide Value 3 = Address + 2 : 4096 1 SV Divider Ratio FT0 FT Divider Ratio MK2069-04 REV J 051310 ...

  • Page 3

    ... Ground connection for internal digital circuitry. Power Lock detector threshold setting circuit connection. Refer to circuit on page 10. — VCXO PLL phase detector Reference Clock output. Ground Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR). 3 VCXO AND SYNTHESIZER Pin Description MK2069-04 REV J 051310 ...

  • Page 4

    ... SV1 56 RPV Functional Description The MK2069- PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to an input reference clock. It contains two cascaded PLL’s with user selectable divider ratios. The first PLL is VCXO-based and uses an external pullable crystal as part of the normal “VCO” (voltage controlled oscillator) function of the PLL ...

  • Page 5

    ... MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Application Information The MK2069- mixed analog / digital integrated circuit that is sensitive to PCB (printed circuit board) layout and external component selection. Used properly, the device will provide the same high performance expected from a canned VCXO-based hybrid timing device, but at a lower cost ...

  • Page 6

    ... Notes on setting the value Divider As another general rule, the following relationship should be maintained between components C filter: in loop filter in Farads S 6 VCXO AND SYNTHESIZER Refer to "Crystal Tuning Load 6 Capacitors" Section Crystal Tuning Capacitors XTAL LFR ISET SET and C S MK2069- the loop P REV J 051310 ...

  • Page 7

    ... As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from IDT, increasing charge pump current (I both bandwidth and damping factor. 7 VCXO AND SYNTHESIZER is to use the filter P should be increased in value until it P 10E+6 Recommended Range of Operation ) increases CP MK2069-04 REV J 051310 is too P ...

  • Page 8

    ... F 4 680 4 128 VCXO AND SYNTHESIZER equal to the input frequency divided PD should be typically at least PD Loop Loop Passband Note BW Damp. Peaking (-3dB) 4.0 0.15dB at 1Hz 1 1.4 1.2dB at 6Hz 2 4.5 0.12dB at 1Hz 0.85 1.8dB at 8Hz 4 MK2069-04 , also needs to PD REV J 051310 ...

  • Page 9

    ... TCLK is always locked to VCLK regardless of the state of the CLR input. Lock Detection The MK2069-04 includes a lock detection feature that indicates lock status of VCLK relative to the selected input reference clock. When phase lock is achieved (such as following power-up), the LD output goes high. When phase ...

  • Page 10

    ... RLD and CLD components but the LD output will not be used, RLD can remain unstuffed and CLD can be replaced with a resistor (< 10 kohm). Power Supply Considerations As with any integrated clock device, the MK2069-04 has a special set of power supply requirements: • The feed from the system power supply must be filtered for noise that can cause output clock jitter ...

  • Page 11

    ... MK2069-04 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF. To achieve this, the layout should use short traces between the MK2069-04 and the crystal. IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Recommended Crystal Parameters: Crystal parameters can be found in application note MAN05 on www ...

  • Page 12

    ... In applications that especially sensitive to noise, such as SONET or G-Bit ethernet transceivers, some or all of the following crystal shielding techniques should be considered. This is especially important when the MK2069-04 is placed near high speed logic or signal traces. The following techniques are illustrated on the Recommended PCB Layout drawing. ...

  • Page 13

    ... If output LD is not used, RLD and CLD may be (film type) 13 VCXO AND SYNTHESIZER CBD G A CBB G 603 603 MK2069 RLD G 38 603 37 CLD 36 603 External loop capacitor C (film type External loop resistor R S current value 33 omitted. See text on page 10. MK2069- 603 RT 603 G REV J 051310 ...

  • Page 14

    ... LDR pin. Use RCLK as the scope trigger. LDR will produce a negative pulse equal in length to the charge pump pulse. 3.5) Filter leakage can also be caused by the use of improper loop capacitors. Refer to the section titled ‘Loop Filter Capacitor Type’ on page 9. 14 VCXO AND SYNTHESIZER /20 MK2069-04 REV J 051310 ...

  • Page 15

    ... VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2069-04. These ratings, which are standard values for IDT industrial rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...

  • Page 16

    ... VDD, providing utility in hot-plug line card IH 16 VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. VDD + V 0.4 -0.4 0.8 V 200 k VDD/2+1 VDD + V 0.4 VDD/2+1 5.5 V -0.4 VDD/2-1 V -10 +10 A -10 + VDD-0.4 V 2.4 V 0.4 V ±50 mA ± VDD V MK2069-04 REV J 051310 ...

  • Page 17

    ... Measured at VDD/ = Measured at VDD/ = Measured at VDD/ = VCXO AND SYNTHESIZER Min. Typ. Max. Units 13.5 27 MHz ±115 ±150 ppm -300 -150 ppm 0.008 170 MHz 0.002 160 MHz 10 nsec 0.001 27 MHz 0 320 MHz 105 0.5 VCLK Period MK2069-04 REV J 051310 ...

  • Page 18

    ... VCXO PLL loop filter. IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Symbol Conditions t 0 2 0 2 Rising edges Rising edges Rising edges OUT 18 VCXO AND SYNTHESIZER Min. Typ. Max. Units 2 1.5 + MK2069-04 REV J 051310 ...

  • Page 19

    ... MK2069-04GILF MK2069-04GILF MK2069-04GILFTR MK2069-04GILF "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied ...

  • Page 20

    ... MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc ...