MK2069-04GILF IDT, Integrated Device Technology Inc, MK2069-04GILF Datasheet - Page 11

• Manufacturer Part Number: MK2069-04GILF
• Description: IC CLOCK SYNTHESIZER 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-04GILF

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Number Of Elements: 2
• Supply Current: 30mA
• Pll Input Freq (min): 1KHz
• Pll Input Freq (max): 170MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: 0.5 to 160MHz
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Industrial
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1783; 800-1783-5; 800-1783

Recommended Power Supply Connection
Series Termination Resistor
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to reduce
EMI. To series terminate a 50 trace, which is a commonly
used PCB trace impedance, place a 33 resistor in series
with the clock line as close to the clock output pin as
possible. The nominal impedance of the clock output is 20 .
Quartz Crystal
The MK2069-04 operates by phase-locking the VCXO
circuit to the input signal at the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters must be used, and the layout guidelines
discussed in the following section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the load capacitors connected to it. The
MK2069-04 incorporates variable load capacitors on-chip
which “pull” or change the frequency of the crystal. The
crystals specified for use with the MK2069-04 are designed
to have zero frequency error when the total of on-chip +
stray capacitance is 14 pF. To achieve this, the layout should
use short traces between the MK2069-04 and the crystal.
IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Connection Via to 3.3V
Power Plane
Ferrite
Chip
VDD
Pin
VDD
Pin
VDD
Pin
VDD
Pin
11
Recommended Crystal Parameters:
Crystal parameters can be found in application note MAN05
on www.idt.com. Approved crystals can be found at
www.idt.com (search “crystal”).
Crystal Tuning Load Capacitors
The crystal traces should include pads for small capacitors
from X1 and X2 to ground, shown as C
VCXO PLL Components diagram on page 6. These
capacitors are used to center the total load capacitor
adjustment range imposed on the crystal. The load
adjustment range includes stray PCB capacitance that
varies with board layout. Because the typical telecom
reference frequency is accurate to less than 32 ppm, the
MK2069-04 may operate properly without these adjustment
capacitors. However, IDT recommends that these
capacitors be included to minimize the effects of variation in
individual crystals, including those induced by temperature
and aging. The value of these capacitors (typically 0-4 pF)
is determined once for a given board layout, using the
procedure described in MAN05.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed. Please
refer to the Recommended PCB Layout drawing on the
following page.
1) Each 0.01µF decoupling capacitor (CD) should be
mounted on the component side of the board as close to the
VDD pin as possible. No via’s should be used between the
decoupling capacitor and VDD pin. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via. Distance of the ferrite chip and bulk
decoupling from the device is less critical.
2) The loop filter components must also be placed close to
the CHGP and VIN pins. C
Coupling of noise from other system signal traces should be
minimized by keeping traces short and away from active
signal traces. Use of vias should be avoided.
3) The external crystal should be mounted as close the
device as possible, on the component side of the board.
This will keep the crystal PCB traces short which will
minimize parasitic load capacitance on the crystal and as
well as noise pickup. The crystal traces should be spaced
away from each other and should use minimum trace width.
P
should be closest to the device.
VCXO AND SYNTHESIZER
MK2069-04
L
in the External
REV J 051310