MPC93R51ACR2 IDT, Integrated Device Technology Inc, MPC93R51ACR2 Datasheet

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MPC93R51ACR2

Manufacturer Part Number
MPC93R51ACR2
Description
IC PLL CLK DRIVER LV 32-LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet

Specifications of MPC93R51ACR2

Pll
Yes with Bypass
Input
LVCMOS, LVPECL
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
2:9
Differential - Input:output
Yes/No
Frequency - Max
240MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
240MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
MPC93R51ACR2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Low Voltage PLL Clock Driver
Freescale Semiconductor
Technical Data
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage PLL Clock Driver
high performance clock distribution systems. With output frequencies of up to
240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal
solution for the most demanding clock tree designs. The device offers 9 low skew
clock outputs, each is configurable to support the clocking needs of the various
high-performance microprocessors including the PowerQuicc II integrated
communication microprocessor. The devices employ a fully differential PLL
design to minimize cycle-to-cycle and long-term jitter.
Features
Functional Description
operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback
path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be
selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of
the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs
is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using
the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2
and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input
(TCLK). The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test
mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended
for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification
does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes
the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase
locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is 3.3 V compatible and requires no external
loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the
MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a
7x7 mm
Application Information
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase
offset between the outputs and the reference signal.
Freescale Confidential Proprietary, NDA Required / Preliminary
The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for
The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with
25–240 MHz output frequency range
Fully integrated PLL
Compatible to various microprocessors such as PowerQuicc II
Supports networking, telecommunications and computer applications
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
LVPECL and LVCMOS compatible inputs
External feedback enables zero-delay configurations
Output enable/disable and static test mode (PLL enable/disable)
Low skew characteristics: maximum 150 ps output-to-output
Cycle-to-cycle jitter max. 22 ps RMS
32-lead LQFP package
32-lead Pb-free Package Available
Ambient Temperature Range 0°C to +70°C
Pin & Function Compatible with the MPC951
9 outputs LVCMOS PLL clock generator
2
32-lead LQFP package.
1
PLL CLOCK GENERATOR
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
LOW VOLTAGE 3.3 V
Pb-FREE PACKAGE
CASE 873A-03
CASE 873A-03
FA SUFFIX
AC SUFFIX
DATA SHEET
Rev. 4, 1/2005
MPC93R51
MPC93R51
MPC93R51

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MPC93R51ACR2 Summary of contents

Page 1

Freescale Semiconductor Technical Data Low Voltage PLL Clock Driver Low Voltage PLL Clock Driver The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies 240 MHz ...

Page 2

MPC93R51 Low Voltage PLL Clock Driver (Pullup) PCLK PCLK (Pulldown) TCLK (Pulldown) REF_SEL (Pulldown) EXT_FB (Pullup) PLL_EN (Pulldown) FSELA (Pulldown) FSELB (Pulldown) FSELC (Pulldown) FSELD (Pulldown) OE The MPC93R51 requires an external RC filter for the analog power supply pin ...

Page 3

MPC93R51 Low Voltage PLL Clock Driver Table 1. Pin Description Number Name PCLK, PCLK Input TCLK Input EXT_FB Input REF_SEL Input FSELA Input FSELB Input FSELC Input FSELD Input OE Input QA Output QB Output QC0, QC1 Output QD0 – ...

Page 4

MPC93R51 Low Voltage PLL Clock Driver Table 4. General Specifications Symbol Characteristics V Output Termination Voltage TT MM ESD (Machine Model) HBM ESD (Human Body Model) LU Latch-Up C Power Dissipation Capacitance Table 5. DC Characteristics (V ...

Page 5

MPC93R51 Low Voltage PLL Clock Driver Table 6. AC Characteristics (V CC Symbol Characteristics (2) f Input Frequency ref f VCO Frequency VCO f Maximum Output Frequency MAX f Reference Input Duty Cycle refDC V Peak-to-Peak Input Voltage PP (3) ...

Page 6

MPC93R51 Low Voltage PLL Clock Driver Programming the MPC93R51 The MPC93R51 clock driver outputs can be configured into several divider modes. In addition, the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. ...

Page 7

MPC93R51 Low Voltage PLL Clock Driver Calculation of Part-to-Part Skew The MPC93R51 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (TCLK or PCLK) of two or more ...

Page 8

MPC93R51 Low Voltage PLL Clock Driver 0.1 µ 0.1 µF Figure 6. V Power Supply Filter CCA As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins ...

Page 9

MPC93R51 Low Voltage PLL Clock Driver 3.0 OutA 2 3.8956 2.0 In 1.5 1.0 0 TIME (ns) Figure 8. Single versus Dual Waveforms Pulse Generator Z = 50Ω Figure 10. TCLK ...

Page 10

MPC93R51 Low Voltage PLL Clock Driver PCLK PCLK Ext_FB t (∅) Figure 12. Propagation Delay (t Offset) Test Reference The time from the PLL controlled edge to the non controlled edge, divided by ...

Page 11

MPC93R51 Low Voltage PLL Clock Driver D1/2 PIN 1 INDEX E1 D/2 4X 0. 28X SEATING PLANE (S) A1 DETAIL AD IDT™ Low ...

Page 12

MPC92459 MPC93R51 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer Low Voltage PLL Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters ...

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