ICS951413CGLF IDT, Integrated Device Technology Inc, ICS951413CGLF Datasheet - Page 10

• Manufacturer Part Number: ICS951413CGLF
• Description: IC SYSTEM CLOCK CHIP P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of ICS951413CGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 951413CGLF

0929D—10/30/06
NOTE: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output.
SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register
SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register
SMBus Table: Output Drive and ATIG Frequency Control Register
NOTE: CPU(1:2)_Stop_En (Byte5, bit 6:5) only exist in devices with REV ID = 2 or higher
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 3
Byte 4
Byte 5
Behavior of the device is undefined under these conditions.
CPU, SRC,
Integrated
Circuit
Systems, Inc.
12,13
16,17
18,19
22,23
24,25
34,33
24,25
34,33
12,13
16,17
18,19
22,23
27,28
30,29
41,40
43,42
ATIG
52
4
-
-
-
-
-
Pin #
Pin #
Pin #
Output Disable
CPU2_Stop_En
CPU1_Stop_En
REQASRC3
REQASRC0
REQASRC7
REQASRC6
REQASRC5
REQASRC4
Differential
USB_48Str
ATIGCLK1
ATIGCLK0
SRCCLK7
SRCCLK6
SRCCLK5
SRCCLK4
SRCCLK3
SRCCLK0
(SS_EN)
REF2Str
SRCFS4
SRCFS3
SRCFS2
SRCFS1
SRCFS0
Name
Name
Name
Mode
48MHz Strength Control RW
1 = CPU is stopped by
Master Output control.
These outputs cannot
REF2 Strength Control
CLKREQA# Controls
CLKREQA# Controls
CLKREQA# Controls
CLKREQA# Controls
CLKREQA# Controls
CLKREQA# Controls
output, regardless of
Hi-Z or driven when
Enables or disables
0 = CPU is free-run
Control Function
Control Function
Control Function
CLKREQ# inputs.
Freq Select Bit 4
be controlled by
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
CLKREQ# pins.
Output Enable
CPU_STOP#
(SS_EN)
disabled
SRC3
SRC0
SRC7
SRC6
SRC5
SRC4
10
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Does not
Does not
Does not
Does not
Does not
Does not
Free-Run
Free-Run
Disabled
Disabled
Disable
Disable
Disable
Disable
Disable
Disable
Frequency Selection
control
control
control
control
control
control
Driven
See Table 2 SRC
1X
1X
0
0
0
Stoppable
Stoppable
Controls
Controls
Controls
Controls
Controls
Controls
Enabled
Enabled
Enable
Enable
Enable
Enable
Enable
Enable
Hi-Z
2X
2X
1
1
1
ICS951413
PWD
PWD
PWD
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1