ICS951413CGLF IDT, Integrated Device Technology Inc, ICS951413CGLF Datasheet - Page 15

• Manufacturer Part Number: ICS951413CGLF
• Description: IC SYSTEM CLOCK CHIP P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of ICS951413CGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 951413CGLF

Absolute Max
0929D—10/30/06
1
2
3
Electrical Characteristics - Input/Supply/Common Output Parameters
T
Low-level Output Voltage
ppm frequency accuracy on PLL outputs.
Tambient
ESD prot
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
Symbol
VDD_In
VDD_A
A
Modulation Frequency
Clock/Data Rise Time
Tcase
Low Threshold Input-
Low Threshold Input-
Clock/Data Fall Time
Powerdown Current
= 0 - 70°C; Supply Voltage V
Current sinking at
Input High Voltage
Input High Current
Operating Current
Input Capacitance
Input Low Voltage
Input Low Current
Ts
Input Frequency
Clk Stabilization
Pin Inductance
SMBus Voltage
PARAMETER
SCLK/SDATA
SCLK/SDATA
High Voltage
Low Voltage
Tdrive_PD#
V
Trise_Pd#
Tfall_Pd#
OL
Integrated
Circuit
Systems, Inc.
= 0.4 V
3.3V Logic Input Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Storage Temperature
Input ESD protection
human body model
Case Temperature
Parameter
SYMBOL
I
I
I
V
V
DD3.3OP
DD3.3PD
T
C
PULLUP
T
C
T
V
V
V
V
I
I
IH_FS
L
C
IL_FS
STAB
I
RI2C
IL1
IL2
F
OUT
FI2C
IH
INX
pin
DD
OL
IH
IL
IN
i
DD
= 3.3 V +/-5%
V
V
all differential pairs tri-stated
assertion of PD# to 1st clock
From V
IN
IN
CPU output enable after
Output pin capacitance
= 0 V; Inputs with no pull-
= 0 V; Inputs with pull-up
Triangular Modulation
(Min VIH + 0.15) to
(Max VIL - 0.15) to
all diff pairs driven
all outputs driven
PD# de-assertion
(Min VIH + 0.15)
(Max VIL - 0.15)
PD# rise time of
PD# fall time of
CONDITIONS
X1 & X2 pins
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
up resistors
3.3 V +/-5%
3.3 V +/-5%
V
DD
V
@ I
GND - 0.5
resistors
DD
IN
Power-Up or de-
2000
= 3.3 V
Min
= V
PULLUP
-65
0
DD
V
V
DD
DD
Max
150
115
+ 0.5V
+ 0.5V
70
15
V
V
SS
SS
-200
MIN
0.7
2.7
30
-5
-5
2
4
- 0.3
- 0.3
Units
°C
°C
°
V
V
V
C
14.31818
TYP
V
V
DD
DD
MAX
1000
0.35
400
300
300
0.8
1.8
5.5
0.4
70
12
33
+ 0.3
5
+ 0.3
7
5
6
5
5
5
UNITS Notes
MHz
kHz
mA
mA
mA
mA
ms
uA
uA
uA
nH
pF
pF
pF
us
ns
ns
ns
ns
V
V
V
V
V
V
1,2
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
2
1
1
1
1
1
ICS951413