ICS951413CGLF IDT, Integrated Device Technology Inc, ICS951413CGLF Datasheet - Page 3

• Manufacturer Part Number: ICS951413CGLF
• Description: IC SYSTEM CLOCK CHIP P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of ICS951413CGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 951413CGLF

Pin Description (Continued)
0929D—10/30/06
PIN #
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34
35
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38
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43
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46
47
48
49
50
51
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54
55
56
Integrated
Circuit
Systems, Inc.
ATIGCLKC0
ATIGCLKT0
GNDATI
VDDATI
SRCCLKC0
SRCCLKT0
VDDSRC
GNDSRC
IREF
GNDA
VDDA
CPUCLKC2_ITP
CPUCLKT2_ITP
CPUCLKC1
CPUCLKT1
GNDCPU
VDDCPU
CPUCLKC0
CPUCLKT0
*CPU_STOP#
GNDPCI
**CK410#/PCICLK0
VDDPCI
**TEST_SEL/REF2
**FS_B/REF1
**FS_A/REF0
GND
VDDREF
PIN NAME
TYPE
PWR Ground for ATI Gclocks, nominal 3.3V
PWR Power supply ATI Gclocks, nominal 3.3V
PWR Supply for SRC clocks, 3.3V nominal
PWR Ground pin for the SRC outputs
PWR Ground pin for the PLL core.
PWR 3.3V power for the PLL core.
PWR Ground pin for the CPU outputs
PWR Supply for CPU clocks, 3.3V nominal
PWR Ground pin for the PCI outputs
PWR Power supply for PCI clocks, nominal 3.3V
PWR Ground pin.
PWR Ref, XTAL power supply, nominal 3.3V
OUT Complementary clock of differential ATIGCLK clock pair.
OUT True clock of differential ATIGCLK clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PIN
I/O
I/O
I/O
I/O
IN
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Stops all CPUCLK, except those set to be free running clocks
FS Table select latch input pin / 3.3V PCI clock output.
0 = CK410 FS Table, 1 = CK409 FS Table
TEST_SEL: latched input to select TEST MODE / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
1 = All outputs are CK410 REF/N test mode
0 = All outputs behave normally.
3
Pin Description
ICS951413