ICS932S421CFLF IDT, Integrated Device Technology Inc, ICS932S421CFLF Datasheet
ICS932S421CFLF
Specifications of ICS932S421CFLF
Related parts for ICS932S421CFLF
ICS932S421CFLF Summary of contents
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Integrated Circuit Systems, Inc. PCIe Gen 2 and QPI Clock for Intel-based Servers Recommended Application: PCIe Gen 2 & QPI compliant CK410B+ clock for Intel-based servers Output Features: • 0.7V current-mode differential CPU pairs • 0.7V ...
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Integrated Circuit Systems, Inc. Pin Description Pin # PIN NAME 1 VDDPCI 2 GNDPCI 3 PCICLK0 4 PCICLK1 5 PCICLK2 6 PCICLK3 7 GNDPCI 8 VDDPCI 9 PCICLK_F0 10 PCICLK_F1 11 PCICLK_F2 12 VDD48 13 48MHz 14 GND48 15 VDDSRC ...
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Integrated Circuit Systems, Inc. Pin Description (Continued) Pin # PIN NAME 29 SCLK 30 SDATA 31 Vtt_PwrGd#/ IREF 34 GNDA 35 VDDA 36 CPUCLKC3 37 CPUCLKT3 38 VDDCPU 39 CPUCLKC2 40 CPUCLKT2 41 GNDCPU 42 CPUCLKC1 43 ...
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Integrated Circuit Systems, Inc. General Description The ICS932S421C is a main clock synthesizer for CK410B+ generation Intel server platforms. The ICS932S421C is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and PCI-Express clocks at 100 or ...
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Integrated Circuit Systems, Inc. Single-ended Output Terminations ICS932S421C SEPP Output Buffer (Single Ended Push Pull) SEPP Output Buffer (Single Ended Push Pull) The singled-ended outputs of the ICS 932S421C default to a drive strength of 2 loads. The REF clocks ...
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Integrated Circuit Systems, Inc. Absolute Maximum Rating PARAMETER SYMBOL 3.3V Core Supply Voltage VDD_A 3.3V Logic Input Supply VDD_In Voltage Storage Temperature Ts Ambient Operating Temp Tambient Case Temperature Tcase Input ESD protection HBM ESD prot 1 Guaranteed by design ...
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Integrated Circuit Systems, Inc. Electrical Characteristics - CPU 0.7V Current Mode Differential Pair PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage Low VLow Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx ...
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Integrated Circuit Systems, Inc. Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL Long Accuracy ppm Clock period T period Absolute Clock period T pabs Clock period w/spread T periodSS Absolute Clock period T pabsSS w/spread Clock High Time T HIGH Clock Low ...
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Integrated Circuit Systems, Inc. Electrical Characteristics - USB48MHz PARAMETER SYMBOL Long Accuracy ppm Clock period T period Absolute Clock period T pabs Output Impedance R DSP Output High Voltage V OH Clock High Time T HIGH Clock Low Time T ...
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Integrated Circuit Systems, Inc. Electrical Characteristics - REF PARAMETER SYMBOL Long Accuracy ppm Clock period T period Absolute Clock period T pabs Clock High Time T HIGH Clock Low Time T LOW Output High Voltage V OH Output Low Voltage ...
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Integrated Circuit Systems, Inc. Differential Clock AC Tolerances CPU PPM tolerance 100 Cycle to Cycle Jitter 50 Spread -0.50% Clock Periods - Differential Outputs with Spread Spectrum Disabled 1 Clock Center SSC ON Freq. -c2c jitter Short-Term MHz AbsPer Min ...
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Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS932S421C How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the ...
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Integrated Circuit Systems, Inc. SMBus Table: Output Enable Register Byte 0 Pin # NA SRCCLK7 Enable Bit 7 NA SRCCLK6 Enable Bit 6 NA SRCCLK5 Enable Bit 5 26,27 SRCCLK4 Enable Bit 4 23,24 SRCCLK3 Enable Bit 3 21,22 SRCCLK2 ...
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Integrated Circuit Systems, Inc. SMBus Table: Stop and Power Down Mode Drive Control Register Byte 4 Pin # CPUCLK3 PD Drive Bit 7 36,37 CPUCLK2 PD Drive Bit 6 39,40 CPUCLK1 PD Drive Bit 5 42,43 45,46 CPUCLK0 PD Drive ...
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Integrated Circuit Systems, Inc. SMBus Table: Byte Count Register Byte 8 Pin # - Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 SMBus Table: Device ...
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Integrated Circuit Systems, Inc. SMBus Table: CPU Frequency Control Register Byte 11 Pin # - CPU N Div8 Bit 7 - CPU N Div9 Bit 6 - CPU M Div5 Bit 5 - CPU M Div4 Bit 4 - CPU ...
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Integrated Circuit Systems, Inc. SMBus Table: SRC/PCI Frequency Control Register Byte 15 Pin # - SRC N Div8 Bit 7 - SRC N Div9 Bit 6 - SRC M Div5 Bit 5 - SRC M Div4 Bit 4 - SRC ...
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Integrated Circuit Systems, Inc. SMBus Table: CPU Programmable Output Divider Register Byte 19 Pin # - CPUDiv3 Bit 7 - CPUDiv2 Bit 6 - CPUDiv1 Bit 5 - CPUDiv0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus ...
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Integrated Circuit Systems, Inc. PD, Power Down asynchronous active high input used to shut off all clocks cleanly prior to system power down. When PD is asserted, all clocks will be driven low before turning off the ...
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Integrated Circuit Systems, Inc. PD De-assertion The time from the de-assertion until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to '1' ...
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Integrated Circuit Systems, Inc INDEX INDEX AREA AREA 45° 45° 1460E—08/25/09 c SYMBOL ...
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Integrated Circuit Systems, Inc INDEX INDEX AREA AREA Ordering Information Part / Order Number Shipping Packaging 932S421CFLF 932S421CFLFT Tape and Reel 932S421CGLF 932S421CGLFT Tape and Reel “LF” ...
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Integrated Circuit Systems, Inc. Revision History Rev. Issue Date Description A 4/15/2008 Initial Release B 9/17/2008 Updated electrical characteristics, PPM and clock period data C 11/20/2008 Added 48MHz electrical char table. Corrected Byte 10 bits 4 and 5 to reserved. ...