ICS932S421CFLF IDT, Integrated Device Technology Inc, ICS932S421CFLF Datasheet - Page 3

• Manufacturer Part Number: ICS932S421CFLF
• Description: IC PCIE GEN2 MAIN CLOCK 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS932S421CFLF

• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output: -
• Input: -
• Other names: 932S421CFLF

Pin Description (Continued)
1460E—08/25/09
Pin #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Integrated
Circuit
Systems, Inc.
SCLK
SDATA
Vtt_PwrGd#/PD
NC
IREF
GNDA
VDDA
CPUCLKC3
CPUCLKT3
VDDCPU
CPUCLKC2
CPUCLKT2
GNDCPU
CPUCLKC1
CPUCLKT1
VDDCPU
CPUCLKC0
CPUCLKT0
VDDCPU
FS_A
FS_B/TEST_MODE
GNDREF
X2
X1
VDDREF
REF1
REF0
FS_C/TEST_SEL
PIN NAME
Type
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
N/A
I/O
IN
IN
IN
IN
IN
IN
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to
be sampled. PD is an asynchronous active high input pin used to put the device into a
low power state. The internal clocks, PLLs and the crystal oscillator are stopped.
No Connection.
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Ground pin for the CPU outputs
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values.
for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z
and REF/N divider mode while in test mode. Refer to Test Clarification Table.
Ground pin for the REF outputs.
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
14.318 MHz reference clock.
input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see
3
Pin Description
ICS932S421C