MPC9772AE IDT, Integrated Device Technology Inc, MPC9772AE Datasheet

MPC9772AE

Manufacturer Part Number

MPC9772AE

Description

IC PLL CLK GEN 1:12 3.3V 52-LQFP

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Generatorr

Datasheet

1.MPC9772AER2.pdf (16 pages)

Specifications of MPC9772AE

Pll

Yes with Bypass

Input

LVCMOS, Crystal

Output

LVCMOS

Number Of Circuits

Ratio - Input:output

2:18

Differential - Input:output

No/No

Frequency - Max

240MHz

Divider/multiplier

Yes/No

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

52-LQFP

Frequency-max

240MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Part Number:

MPC9772AER2

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3.3V 1:12 LVCMOS PLL

CLOCK GENERATOR

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

3.3 V 1:12 LVCMOS PLL Clock

Generator

for high performance low-skew clock distribution in mid-range to

high-performance networking, computing and telecom applications. With output

frequencies up to 240 MHz and output skews less than 250 ps the device meets

the needs of the most demanding clock applications.

Features

•

Functional Description

MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The

reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match

the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as

well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8:3.

feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference

versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-

tion the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-

binary factor. The MPC9772 also supports the 180° phase shift of one of its output banks with respect to the other output banks.

The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of sys-

tem baseline timing signals.

alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL

bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output

dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL char-

acteristics do not apply.

MPC9772. The MPC9772 has an internal power-on reset.

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission

lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an

effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package.

The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted

The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two

The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the

The MPC9772 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept

1:12 PLL Based Low-Voltage Clock Generator

3.3 V Power Supply

Internal Power-On Reset

Generates Cock Signals Up to 240 MHz

Maximum Output Skew of 250 ps

On-Chip Crystal Oscillator Clock Reference

Two LVCMOS PLL Reference Clock Inputs

External PLL Feedback Supports Zero-Delay Capability

Various Feedback and Output Dividers (See

Section)

Supports Up to Three Individual Generated Output Clock Frequencies

Synchronous Output Clock Stop Circuitry for Each Individual Output for

Power Down Support

Drives Up to 24 Clock Lines

Ambient Temperature Range 0°C to +70°C

Pin and Function Compatible To the MPC972

52-Lead Pb-Free Package Available

Applications Information

PLL CLOCK GENERATOR

52-LEAD LQFP PACKAGE

3.3 V 1:12 LVCMOS

MPC9772 REV 6 FEBRUARY 7, 2007

Pb-FREE PACKAGE

MPC9772

CASE 848D-03

FA SUFFIX

AE SUFFIX

MPC9772

Related parts for MPC9772AE

MPC9772AE Summary of contents

Page 1

LVCMOS PLL CLOCK GENERATOR 3.3 V 1:12 LVCMOS PLL Clock Generator The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom ...

Page 2

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR All input resistors have a value of 25kΩ XTAL_IN XTAL 1 XTAL_OUT CCLK0 0 1 CCLK1 CCLK_SEL V CC REF_SEL FB_IN VCO_SEL PLL_EN V CC FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] V ...

Page 3

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 1. Pin Configuration Pin I/O CCLK0 Input LVCMOS PLL reference clock CCLK1 Input LVCMOS Alternative PLL reference clock XTAL_IN, XTAL_OUT FB_IN Input LVCMOS PLL feedback signal input, connect to an QFB CCLK_SEL ...

Page 4

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 2. Function Table (Configuration Controls) Control Default REF_SEL 1 Selects CCLKx as the PLL reference clock CCLK_SEL 1 Selects CCLK0 VCO_SEL 1 Selects VCO÷2. The VCO frequency is scaled by a factor ...

Page 5

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 5. Output Divider Bank C (N VCO_SEL Table 6. Output Divider PLL Feedback (M) VCO_SEL FSEL_FB2 ...

Page 6

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 9. DC Characteristics (V CC Symbol Characteristics V PLL Supply Voltage CC_PLL V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output Low Voltage OL ...

Page 7

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 10. AC Characteristics (V Symbol Characteristics t Propagation Delay (static phase offset) (∅) CCLK to FB_IN 6.25 MHz < f 65.0 MHz < =50 MHz and feedback=÷8 REF (8) t ...

Page 8

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR MPC9772 Configurations Configuring the MPC9772 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: ⋅ M ÷ ...

Page 9

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR CCLK0 QA[3: 33.3 MHz CCLK1 ref CCLK_SEL QB[3:0] 1 VCO_SEL FB_IN FSEL_A[1:0] 11 QC[3:0] 00 FSEL_B[1:0] 00 FSEL_C[1:0] 101 FSEL_FB[2:0] MPC9772 33.3 MHz (Feedback) MPC9772 example configuration (feedback of QFB = ...

Page 10

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR f VCO QA QC QSYNC QA QC QSYNC QC(÷2) QA(÷6) QSYNC QA(÷4) QC(÷6) QSYNC QC(÷2) QA(÷8) QSYNC QA(÷6) QC(÷8) QSYNC QA(÷12) QC(÷2) QSYNC IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR 1:1 ...

Page 11

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Power Supply Filtering The MPC9772 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on ...

Page 12

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Due to the statistical nature of I/O jitter a RMS value (1 σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. Table 12. Confidence Factor ...

Page 13

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR MPC9772 Output Buffer = 36 Ω 14Ω In MPC9772 Output = 36 Ω R Buffer S 14Ω Ω Figure 12. Single versus Dual Transmission Lines The ...

Page 14

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR t SK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 16. Output-to-Output Skew ...

Page 15

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR 4X 0.20 (0.008 -H- -T- SEATING PLANE 0.05 (0.002 VIEW AA IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK ...

Page 16

MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...

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