MK2049-34SAITR IDT, Integrated Device Technology Inc, MK2049-34SAITR Datasheet - Page 5

• Manufacturer Part Number: MK2049-34SAITR
• Description: IC VCXO PLL CLK SYNTH 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Synthesizerr

Specifications of MK2049-34SAITR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 77.76MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 44.736MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PC Board Layout
A proper board layout is critical to the successful use of the MK2049-34A. In particular, the CAP1 and CAP2 pins are very
sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and the two
capacitors and resistor must be mounted next to the device as shown below. The capacitor shown between pins 15 and 17,
and the one between pins 4 and 7 are the power supply decoupling capacitors. The high frequency output clocks on pins 8
and 9 should have a series termination of 33 connected close to the pin. Additional improvements will come from keeping
all components on the same side of the board, minimizing vias through other signal layers, and routing other signals away
from the MK2049. You may also refer to application note MAN05 for additional suggestions on layout of the crystal selection.
The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the stray
capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is accurate to
much less than 1 ppm, so the MK2049-34A may lock and run properly even if the board capacitance is not adjusted with
these fixed capacitors. However, IDT recommends that the adjustment capacitors be included to minimize the effects of
variation in individual crystals, temperature, and aging. The value of these capacitors (typically 0 - 4 pF) is determined once
for a given board layout, using the procedure found in application note MAN05.
IDT™ / 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
MK2049-34A
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
Optional -
see text
Figure 2. Typical MK2049-34 Layout
G
V
resist
cap
resist
1
2
3
4
5
6
7
8
9
10
Cutout in ground and power plane.
Route all traces away from this area.
20
19
18
17
16
15
14
13
12
11
5
G
V
resist
V
G
= connect to VDD
= connect to GND
G
resist
cap
VCXO AND SYNTHESIZER
MK2049-34A REV E 051310