3.3 VOLT COMMUNICATIONS CLOCK PLL
Description
The MK2049-45A is a dual Phase-Locked Loop (PLL)
device which can provide frequency synthesis and jitter
attenuation. The first PLL is VCXO based and uses a
pullable crystal to track signal wander and attenuate input
jitter. The second PLL is a translator for frequency
multiplication. Basic configuration is determined by a
Mode/Frequency Selection Table. Loop bandwidth and
damping factor are programmable via external loop filter
component selection.
Buffer Mode accepts a 10 to 50 MHz input and will provide
a jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x
ICLK. In this mode the MK2049-45A is ideal for filtering jitter
from high frequency clocks.
In External Mode, ICLK accepts an 8 kHz clock and will
produce output frequencies from a table of common
communciations clock rates, CLK and CLK/2. This allows
for the generation of clocks frequency-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems.
The MK2049-45A can be dynamically switched between T1,
E1, T3, E3 outputs with the same 24.576 MHz crystal.
IDT can customize these devices for many other different
frequencies. Contact your IDT representative for more
details.
Block Diagram
C
S
R
C
SET
P
R
S
ISET
CAP2
Phase
Reference
Detector
Divider
ICLK
(used in buffer
mode only)
VCXO
PLL
4
Divider Value
FS3:0
Look-up Table
IDT™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
Features
•
Packaged in 20-pin SOIC
•
3.3 V + 5% operation
•
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
•
Accepts multiple inputs: 8 kHz backplane clock, or 10 to
50 MHz
•
Locks to 8 kHz + 100 ppm (External mode)
•
Buffer Mode allows jitter attenuation of 10 - 50 MHz input
and x1 / x0.5 or x1 / x2 outputs
•
Exact internal ratios enable zero ppm error
•
Output rates include T1, E1, T3, E3, and OC3
submultiples
•
Pb (lead) free package
•
See also the MK2049-34 and MK2049-36
C
C
Optional Crystal Load Caps
L
L
External Pullable Crystal
CAP1
X1
X2
Reference
VCXO
Divider
Charge
Pump
Feedback
Divider (N)
Translator
PLL
1
DATASHEET
MK2049-45A
Output
VCO
Divider
Divide
by 2
Feedback
Divider
MK2049-45A
CLK
CLK/2
8k
REV C 051310