MK2059-01SILFTR | |
|---|---|
| Manufacturer Part Number | MK2059-01SILFTR |
| Description | IC VCXO CLK JITTER ATTEN 20-SOIC |
| Manufacturer | IDT, Integrated Device Technology Inc |
| Type | Clock Frequency Translator |
| MK2059-01SILFTR datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of MK2059-01SILFTR | |||
|---|---|---|---|
| Pll | Yes | Input | Clock |
| Output | CMOS | Number Of Circuits | 1 |
| Ratio - Input:output | 2:1 | Differential - Input:output | No/No |
| Frequency - Max | 25.92MHz | Divider/multiplier | No/Yes |
| Voltage - Supply | 3.15 V ~ 3.45 V | Operating Temperature | -40°C ~ 85°C |
| Mounting Type | Surface Mount | Package / Case | 20-SOIC |
| Frequency-max | 24.704MHz | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
PrevNext
MK2059-01
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
A “normalized” PLL loop bandwidth may be calculated as
follows:
R
I
575
S
CP
NBW
=
-----------------------------------------
N
The “normalized” bandwidth equation above does not take
into account the effects of damping factor or the second
pole. However, it does provide a useful approximation of
filter performance.
The loop damping factor is calculated as follows:
625
Damping Factor
=
R
------------------------------------------ -
S
Where:
R
= Value of resistor in loop filter (Ohms)
Z
I
= Charge pump current (amps)
CP
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
C
= Value of capacitor C
1
1
As a general rule, the following relationship should be
maintained between components C
filter:
C
S
----- -
=
C
P
20
Charge Pump Current Table
Charge Pump Current
R
(I
)
SET
CP
1.4 M
10 A
680 k
20 A
540 k
25 A
120 k
100 A
IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
Special considerations must be made in choosing loop
components C
found on the IDT web site.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20 . (The
I
C
optional series termination resistor is not shown in the
S
CP
External Component Schematic.)
N
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK2059-01 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
in loop filter (Farads)
MK2059-01 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
and C
in the loop
1
2
modulation.
Recommended Power Supply Connection for
Optimal Device Performance
C onnection to 3.3V
B ulk D ecoupling C apacitor
5
VCXO AND SYNTHESIZER
and C
. These recommendations can be
S
P
Ferrite
Bead
P ow er P lane
(such as 1 F Tantalum )
0.01
F D ecoupling C apacitors
MK2059-01
V D D P in
V D D P in
V D D P in
REV H 051310
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