MK2059-01SITR IDT, Integrated Device Technology Inc, MK2059-01SITR Datasheet - Page 3

• Manufacturer Part Number: MK2059-01SITR
• Description: IC VCXO CLK JITTER ATTEN 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Frequency Translatorr

Specifications of MK2059-01SITR

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/No
• Frequency - Max: 25.92MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 24.704MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
The MK2059-01 is a clock generator IC that generates an
output clock directly from an internal VCXO circuit which
works in conjunction with an external quartz crystal. The
VCXO is controlled by an internal PLL (Phase Locked Loop)
circuit, enabling the device to perform clock regeneration
from an input reference clock. The MK2059-01 is configured
to provide a MHz communications reference clock output
from an 8kHz input clock. There are 12 selectable output
frequencies. Please refer to the Output Clock Selection
Table on Page 2.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK2059-01 is able to
generate a low jitter, low phase-noise output clock within a
low bandwidth PLL. This serves to provide input clock jitter
attenuation and enables stable operation with a low
frequency reference clock.
The VCXO circuit requires an external pullable crystal for
operation. External loop filter components enable a PLL
configuration with low loop bandwidth.
Application Information
Output Frequency Configuration
The MK2059-01 is configured to generate a set of output
frequencies from an 8kHz input clock. Please refer to the
Output Clock Selection Table on Page 2. Input bits SEL2:0
are set according to this table, as is the external crystal
frequency. Please refer to the Quartz Crystal section on this
page regarding external crystal requirements.
Input Mux
The Input Mux serves to select between two alternate input
reference clocks. Upon reselection of the input clock, clock
glitches on the output clock will not be generated due to the
“fly-wheel” effect of the VCXO (the quartz crystal is a high-Q
tuned circuit). When the input clocks are not phase aligned,
the phase of the output clock will change to reflect the phase
of newly selected input at a controlled phase slope (rate of
phase change) as influenced by the PLL loop
characteristics.
IDT™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
MK2059-01
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
3
Quartz Crystal
It is important that the correct type of quartz crystal is used
with the MK2059-01. Failure to do so may result in reduced
frequency pullability range, inability of the loop to lock, or
excessive output phase jitter.
The MK2059-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the PCB Layout Recommendations
section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the external load capacitance. The
MK2059-01 incorporates variable load capacitors on-chip
which “pull”, or change, the frequency of the crystal. The
crystals specified for use with the MK2059-01 are designed
to have zero frequency error when the total of on-chip +
stray capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2059-01 and the crystal.
A complete description of the recommended crystal
parameters is shown in application note MAN05.
A list of qualified crystal devices that meet these
requirements can be found on the IDT web site.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish operating
stability. The MK2059-01 uses external loop filter
components for the following reasons:
1) Larger loop filter capacitor values can be used, allowing
a lower loop bandwidth. This enables the use of lower input
clock reference frequencies and also input clock jitter
attenuation capabilities. Larger loop filter capacitors also
allow higher loop damping factors when less passband
peaking is desired.
2) The loop filter values can be user selected to optimize
loop response characteristics for a given application.
Referencing the External Component Schematic on this
page, the external loop filter is made up of components R
C
therefore influences loop filter characteristics. Tools for
determining loop filter component values are on the IDT web
site.
S
and C
P
. R
SET
establishes PLL charge pump current and
VCXO AND SYNTHESIZER
MK2059-01
REV H 051310
S
,