MK2069-01GITR IDT, Integrated Device Technology Inc, MK2069-01GITR Datasheet

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MK2069-01GITR

Manufacturer Part Number
MK2069-01GITR
Description
IC VCXO CLK SYNCHRONIZER 56TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Synchronizerr
Datasheet

Specifications of MK2069-01GITR

Pll
Yes
Input
LVCMOS
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
3:3
Differential - Input:output
No/No
Frequency - Max
160MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Frequency-max
160MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
Description
The MK2069-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation, and frequency
multiplication or translation. It can accept an unstable, jittery
input clock and provide a de-jittered, low phase noise
output clock at a user determined frequency. The device’s
clock multiplication ratios are user selectable since all major
PLL divider blocks can be configured through device pin
settings. External PLL loop filter components allow tailoring
of the VCXO PLL loop response and therefore the clock
jitter attenuation characteristics.
The MK2069-01 is ideal for line card applications. Its three
input MUX enables selection of the master or slave
(backup) system clocks, as well as a backup local line card
clock. The lock detector (LD) output serves as a clock
status monitor. The clear (CLR) input enables rapid
synchronization to the phase of a newly selected input
clock, while eliminating the generation of extra clock cycles
and wander caused by memory in the PLL feedback divider.
CLR also serves as a temporary holdover function when
kept low.
Block Diagram
IDT® VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
M X 1 :0
IC L K 0
IC L K 1
IC L K 2
C L R
2
0 X
1 0
0 1
R V 1 :0
2
1 ,2 ,4 ,1 2 8
D iv id e r
R V
IS E T
V C X O
P L L
D etector
P hase
L F
L F R
C harge
P um p
F V D iv id e r
X 1
1 -4 0 9 6
P u lla b le
V C X O
F V 1 1 :0
x ta l
12
X 2
1 ,2 ,4 ,6 ,8 ,
1 0 ,1 2 ,1 6
D iv id e r
S V 2 :0
S V
L o c k D e te c to r
L D C
3
1
Features
Input clock frequency of 1 kHz to 170 MHz
Output clock frequency of 500 kHz to 160 MHz
Jitter attenuation of input clock provided by VCXO circuit.
Jitter transfer characteristics user configured through
selection of external loop filter components.
3:1 Input MUX for input reference clocks
PLL lock status output
PLL Clear function allows seamless synchronizing to an
altered input clock phase, virtually eliminating the
generation of wander or extra clock cycles.
VCXO-based clock generation offers very low jitter and
phase noise generation, even with a low frequency or
jittery input clock.
2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies (TCLK).
Device will free-run in the absence of an input clock
based on the VCXO crystal frequency.
56 pin TSSOP package
Single 3.3 V power supply
5 V tolerant inputs on ICLK0 and ICLK1
D iv id e r
R T 1 :0
R T
1 -4
2
L D R
T ra n s la to r
P L L
F T D iv id e r
F T 5 :0
1 -6 4
V C O
6
MK2069-01
D iv id e r
2 ,4 ,8 ,1 6
S T 1 :0
S T
DATASHEET
2
MK2069-01
G N D
V D D
REV K 051310
4
4
V C L K
O E V
T C L K
O E T
R C L K
O E R
L D
O E L

Related parts for MK2069-01GITR

MK2069-01GITR Summary of contents

Page 1

... External PLL loop filter components allow tailoring of the VCXO PLL loop response and therefore the clock jitter attenuation characteristics. The MK2069-01 is ideal for line card applications. Its three input MUX enables selection of the master or slave (backup) system clocks, as well as a backup local line card clock ...

Page 2

... Translator PLL Scaling Divider Selection Table ST1 ST0 VCXO AND SYNTHESIZER Notes 2 For FV addresses 0 to 4094 Divide = Address + 2 : 4096 1 SV Divider Ratio Divider Ratio Divider Notes Ratio 2 For FT addresses Divide = Address + Divider Ratio MK2069-01 REV K 051310 ...

Page 3

... Lock detector threshold setting circuit connection. Refer to circuit on page 10. Ground Digital ground connection. - Lock detector threshold setting circuit connection. Refer to circuit on page 10. Output VCXO PLL phase detector Reference Clock output. Ground Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR). 3 VCXO AND SYNTHESIZER Pin Description MK2069-01 REV K 051310 ...

Page 4

... SV1 56 SV2 Functional Description The MK2069- PLL (phase locked loop) based clock generator that generates output clocks synchronized to an input reference clock. It contains two cascaded PLL’s with user selectable divider ratios. The first PLL is VCXO-based and uses an external pullable crystal as part of the normal “VCO” (voltage controlled oscillator) function of the PLL ...

Page 5

... MK2069-01 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER Application Information The MK2069- mixed analog / digital integrated circuit that is sensitive to PCB (printed circuit board) layout and external component selection. Used properly, the device will provide the same high performance expected from a canned VCXO-based hybrid timing device, but at a lower cost ...

Page 6

... MK2069-01 Loop Response and JItter Attenuation Characteristics The MK2069-01 will reduce the transfer of phase jitter existing on the input reference clock to the output clock. This operation is known as jitter attenuation. The low-pass frequency response of the VCXO PLL loop is the mechanism that provides input jitter attenuation ...

Page 7

... Online tools to calculate loop filter response can be found www.idt.com/?app=calculators&source=support_menu and C in the loop VCXO AND SYNTHESIZER value that would be used for a damping factor S value that is too low use the filter P should be increased in value until it P MK2069- too P REV K 051310 ...

Page 8

... IDT, increasing charge pump current (I both bandwidth and damping factor. IDT® VCXO-BASED LINE CARD CLOCK SYNCHRONIZER (external resistor) SET 1E ohms SET VCXO Gain ( increases CP 8 VCXO AND SYNTHESIZER 10E+6 Recommended Range of Operation ) vs. XTAL Frequency MK2069-01 REV K 051310 3 0 ...

Page 9

... This configuration is used to generate a DS3 clock of 44.768 MHz at the TCLK output. This configuration is GR-1244 compliant. 4) The MK2069-02 or MK2069-04 may be more suitable for this application since the VCXO feedback divider can be increased (>128), enabling a lower bandwidth for improved jitter attenuation. Loop Filter Capacitor Type Loop filters must use specific types of capacitors ...

Page 10

... TCLK is always locked to VCLK regardless of the state of the CLR input. Lock Detection The MK2069-01 includes a lock detection feature that indicates lock status of VCLK relative to the selected input reference clock. When phase lock is achieved (such as following power-up), the LD output goes high. When phase ...

Page 11

... RLD and CLD components but the LD output will not be used, RLD can remain unstuffed and CLD can be replaced with a resistor (< 10 kohm). Power Supply Considerations As with any integrated clock device, the MK2069-01 has a special set of power supply requirements: • The feed from the system power supply must be filtered for noise that can cause output clock jitter ...

Page 12

... L and bulk decoupling capacitor may be mounted on the back). Other signal traces should be routed away from the MK2069-01. This includes signal traces on PCB traces just underneath the device layers adjacent to the ground plane layer used by the device. 6) Because each input selection pin includes an internal pull-up device, those inputs requiring a logic high state (“ ...

Page 13

... The crystal should be keep away from these clock sources. The IDT Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. IDT® VCXO-BASED LINE CARD CLOCK SYNCHRONIZER 13 VCXO AND SYNTHESIZER MK2069-01 REV K 051310 ...

Page 14

... If output LD is not used, RLD and CLD may be (film type) 14 VCXO AND SYNTHESIZER CBD G A CBB G 603 603 603 43 MK2069 603 40 39 RLD G 38 603 37 CLD 36 603 (film type used to set charge pump current SET value 33 omitted. See text on page 10. MK2069-01 G REV K 051310 ...

Page 15

... LDR pin. Use RCLK as the scope trigger. LDR will produce a negative pulse equal in length to the charge pump pulse. 3.5) Filter leakage can also be caused by the use of improper loop capacitors. Refer to the section titled ‘Loop Filter Capacitor Type’ on page 9. 15 VCXO AND SYNTHESIZER MK2069-01 REV K 051310 ...

Page 16

... VCXO-BASED LINE CARD CLOCK SYNCHRONIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2069-01. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...

Page 17

... VCLK = 19.44 MHz, TCLK = 155.52 MHz VDD VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. VDD + V 0.4 -0.4 0.8 V 200 k VDD/2+1 VDD + V 0.4 VDD/2+1 5.5 V -0.4 VDD/2-1 V -10 +10 A -10 + VDD-0.4 V 2.4 V 0.4 V ±50 mA ± VDD V MK2069-01 REV K 051310 ...

Page 18

... Measured at VDD/ =15pF L t 0.8 to 2.0V, C =15pF 2.0 to 0.8V, C =15pF VCXO AND SYNTHESIZER Min. Typ. Max. Units 13.5 27 MHz ±115 ±150 ppm -300 -150 ppm 0.001 170 MHz 10 nsec 0.001 27 MHz 0 320 MHz 105 0.5 VCLK Period 1 1 MK2069-01 REV K 051310 ...

Page 19

... VCXO PLL loop filter. IDT® VCXO-BASED LINE CARD CLOCK SYNCHRONIZER Symbol Conditions t 0.8 to 2.0V, C =15pF 2.0 to 0.8V, C =15pF Rising edges, C =15pF Rising edges, C =15pF Rising edges, C =15pF OUT 19 VCXO AND SYNTHESIZER Min. Typ. Max. Units 0. 0. 2 1.5 + MK2069-01 REV K 051310 ...

Page 20

... MK2069-01GILF MK2069-01GILFTR MK2069-01GILF While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied ...

Page 21

... MK2069-01 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc ...

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