MK2069-04GILFTR IDT, Integrated Device Technology Inc, MK2069-04GILFTR Datasheet - Page 18

• Manufacturer Part Number: MK2069-04GILFTR
• Description: IC VCXO CLK TRANSLATOR 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-04GILFTR

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Number Of Elements: 2
• Supply Current: 30mA
• Pll Input Freq (min): 1KHz
• Pll Input Freq (max): 170MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: 0.5 to 160MHz
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Industrial
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although this may
Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1) due to the
Note 3: The minimum practical phase detector frequency is 1 kHz. Through proper loop filter design lower input
Note 4: A higher input clock frequency can be used when RPV divider = 8.
Note 5: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK period.
Note 6: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is present in the
Output Rise Time, VCLK and
RCLK
Output Fall Time, VCLK and
RCLK
Output Rise Time, TCLK
Output Fall Time, TCLK
Skew, ICLK to VCLK (Note 6)
Skew, ICLK to RCLK (Note 6)
Skew, ICLK to TCLK (Note 6)
Nominal Output Impedance
result in increased output phase noise.
attempt of the PLL to lock to 0 Hz.
frequencies may be possible. Input frequencies as low as 400 Hz have been tested.
external VCXO PLL loop filter.
Parameter
Symbol
Z
t
t
t
t
t
OUT
t
t
OR
OF
OR
OF
VT
IV
IV
0.8 to 2.0 V, C
2.0 to 0.8 V, C
0.8 to 2.0 V, C
2.0 to 0.8 V, C
Rising edges, C
Rising edges, C
Rising edges, C
Conditions
18
L
L
L
L
=15 pF
=15 pF
=15 pF
=15 pF
L
L
L
=15 pF
=15 pF
=15 pF
Min.
+5
-5
-5
Typ.
0.75
0.75
1.5
1.5
2.5
1.5
10
20
VCXO AND SYNTHESIZER
MK2069-04
Max. Units
+10
+20
+10
2
2
1
1
ns
ns
ns
ns
ns
ns
ns
REV J 051310