MK2069-04GITR IDT, Integrated Device Technology Inc, MK2069-04GITR Datasheet - Page 4

• Manufacturer Part Number: MK2069-04GITR
• Description: IC VCXO CLK TRANSLATOR 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-04GITR

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
The MK2069-04 is a PLL (Phase Locked Loop) based clock
generator that generates output clocks synchronized to an
input reference clock. It contains two cascaded PLL’s with
user selectable divider ratios.
The first PLL is VCXO-based and uses an external pullable
crystal as part of the normal “VCO” (voltage controlled
oscillator) function of the PLL. The use of a VCXO assures
a low phase noise clock source even when a low PLL loop
bandwidth is implemented. A low loop bandwidth is needed
when the input reference frequency at the phase detector is
low, or when jitter attenuation of the input reference is
desired.
The second PLL is used to translate or multiply the
frequency of the VCXO PLL which has a maximum output
frequency of 27 MHz. This second PLL, or Translator PLL,
uses an on-chip VCO circuit that can provide an output clock
up to 160 MHz. The Translator PLL uses a high loop
bandwidth (typically greater than 1 MHz) to assure stability
of the clock output generated by the VCO. It requires a
stable, high frequency input reference which is provided by
the VCXO.
IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Number
Pin
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Name
VDDP
VCLK
TCLK
OER
VDD
OEV
OET
OEL
RPV
RV2
RV3
RV4
SV0
SV1
Pin
LD
Output
Output
Output
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pin
Clock output from VCXO PLL
Power Supply for output drivers (VCLK, TCLK, RCLK, LD, LDR).
Clock output from Translator PLL
Lock detector output.
Power Supply connection for internal digital circuitry.
Output enable for RCLK. RCLK is tri-stated when low, internal pull-up.
Output enable for VCLK. VCLK is tri-stated when low, internal pull-up.
Output enable for TCLK. TCLK is tri-stated when low, internal pull-up.
Output enable for LD. LD is tri-stated when low, internal pull-up.
Reference Divider bit 2 input, VCXO PLL, internal pull-up.
Reference Divider bit 3 input, VCXO PLL, internal pull-up.
Reference Divider bit 4 input, VCXO PLL, internal pull-up.
Scaler Divider bit 0 input, VCXO PLL, internal pull-up.
Scaler Divider bit 1 input, VCXO PLL, internal pull-up.
RPV divider, VCXO PLL, internal pull-up.
4
The divide values of the divider blocks within both PLLs are
set by device pin configuration. This enables the system
designer to define the following:
•
•
•
•
•
Any unused clock or logic outputs can be tri-stated to reduce
interference (jitter, phase noise) on other clock outputs.
Outputs can also be tri-stated for system testing purposes.
External components are used to configure the VCXO PLL
loop response. This serves to maximize loop stability and to
achieve the desired input clock jitter attenuation
characteristics.
Input clock frequency
VCXO crystal frequency
VCLK output frequency
RCLK output frequency, which is also the phase detector
frequency of the VCXO PLL.
TCLK output frequency
Pin Description
VCXO AND SYNTHESIZER
MK2069-04
REV J 051310