MK2069-03GI IDT, Integrated Device Technology Inc, MK2069-03GI Datasheet - Page 2

• Manufacturer Part Number: MK2069-03GI
• Description: IC VCXO CLK TRANSLATOR 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-03GI

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Number Of Elements: 2
• Supply Current: 30mA
• Pll Input Freq (min): 1KHz
• Pll Input Freq (max): 27MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: 2.5 to 160MHz
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Industrial
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Assignment
VCXO PLL Feedback Pre-Divider Selection
IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 2
FPV5:0 FPV Divider Ratio
000000
000001
111111
MK2069-03
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION
:
G N D V
G N D T
V D D V
V D D T
F P V 0
IS E T
L F R
R T 0
R T 1
S T 0
S T 1
F T 0
F T 1
F T 2
F T 3
F T 4
F T 5
F V 0
F V 1
F V 2
F V 3
F V 4
F V 5
F V 6
F V 7
X 1
X 2
L F
65
2
3
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
:
FPV Divide = Address + 2
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
Notes
S V 2
S V 1
S V 0
F P V 5
F P V 4
F P V 3
O E L
O E T
O E V
O E R
V D D
L D
T C L K
V D D P
V C L K
G N D P
R C L K
L D R
G N D
L D C
C L R
IC L K
F P V 2
F P V 1
F V 1 1
F V 1 0
F V 9
F V 8
VCXO PLL Feedback Divider Selection
VCXO PLL Scaling Divider Selection Table
Translator PLL Reference Divider Selection Table
Translator PLL Feedback Divider Selection
Translator PLL Scaling Divider Selection Table
000000
000001
111110
111111
FV11:0 FV Divider Ratio
SV2 SV1 SV0
RT1 RT0
ST1 ST0
FT5:0
0...00
0...01
1...10
1...11
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
:
:
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FT Divider Ratio
RT Divider Ratio
ST Divider Ratio
0
1
0
1
0
1
0
1
4096
64
2
3
1
:
2
3
1
:
SV Divider Ratio
16
2
3
4
1
2
4
8
10
12
16
For FV addresses 0 to 4094,
4
6
8
2
1
For FT addresses 0 to 62,
FV Divide = Address + 2
FT Divide = Address + 2
VCXO AND SYNTHESIZER
MK2069-03
Notes
Notes
REV J 030906