MK2069-03GI IDT, Integrated Device Technology Inc, MK2069-03GI Datasheet - Page 9

• Manufacturer Part Number: MK2069-03GI
• Description: IC VCXO CLK TRANSLATOR 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-03GI

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Number Of Elements: 2
• Supply Current: 30mA
• Pll Input Freq (min): 1KHz
• Pll Input Freq (max): 27MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: 2.5 to 160MHz
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Industrial
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Loop Filter Capacitor Type
Loop filters must use specific types of capacitors.
Recommendations for these capacitors can be found at
www.idt.com.
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase
compensation circuit. It is used when changing the phase of
the input clock, which might occur when selecting a new
reference input through the use of an external clock
multiplexer.
The phase compensation circuit allows the VCXO PLL to
quickly lock to the new input clock phase without producing
extra clock cycles or clock wander, assuming the new clock
is at the same frequency.
Input pin CLR controls the phase compensation circuit. CLR
must remain high for normal operation. When used in
conjunction with an external multiplexer (MUX), CLR should
be brought low prior to MUX reselection, then returned high
after MUX reselection. This prevents the VCXO PLL from
attempting to lock to the new input clock phase associated
with the input clock.
When CLR is high, the VCXO PLL operates normally.
When CLR is low, the VCXO PLL charge pump output is
inactivated which means that no charge pump correction
pulses are provided to the loop filter. During this time, the
VCXO frequency is held constant by the residual charge or
voltage on the PLL loop filter, regardless of the input clock
condition. However, the VCXO frequency will drift over time,
eventually to the minimum pull range of the crystal, due to
leak-off of the loop filter charge. This means that CLR can
provide a holdover function, but only for a very short
duration, typically in milliseconds.
Upon bringing CLR high, the FV divider is reset and begins
counting with the first positive edge of the new input clock,
and the charge pump is re-activated (FPV is not reset). By
resetting the FV Divider, the memory of the previous input
clock phase is removed from this feedback divider,
eliminating the generation of extra VCLK clock cycles that
would occur if the loop was to re-lock under normal means.
Lock time is also reduced, as is the generation of clock
wander.
IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 9
MK2069-03
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION
By using CLR in this fashion VCLK will align to the input
clock phase with only one or two VCLK cycle slips resulting.
When CLR is not used, the number of VCLK cycle slips can
be as high the FV Divider value.
TCLK is always locked to VCLK regardless of the state of
the CLR input.
Lock Detection
The MK2069-03 includes a lock detection feature that
indicates lock status of VCLK relative to the selected input
reference clock. When phase lock is achieved (such as
following power-up), the LD output goes high. When phase
lock is lost (such as when the input clock stops, drifts beyond
the pullable range of the crystal, or suddenly shifts in
phase), the LD output goes low.
The definition of a “locked” condition is determined by the
user. LD is high when the VCXO PLL phase detector error
is below the user-defined threshold. This threshold is set by
external components RLD and CLD shown in the Lock
Detection Circuit Diagram, below.
To help guard against false lock indications, the LD pin will
go high only when the phase error is below the set threshold
for 8 consecutive phase detector cycles. The LD pin will go
low when the phase error is above the set threshold for only
1 phase detector cycle.
The lock detector threshold (phase error) is determined by
the following relationship:
Lock Detector Application example:
(LD Threshold) = 0.6 x R x C
Where:
The desired maximum allowable loop phase error for a
generated 19.44MHz clock is 100UI which is 5.1 s.
Solution: 5.1 s = (0.001 f) x (8.5 k
1 k < R < 1 M (to avoid excessive noise or leakage)
C > 50 pF (to avoid excessive error due to stray
capacitance, which can be as much as 10 pF
including Cin of LDC)
VCXO AND SYNTHESIZER
MK2069-03
REV J 030906