MK2049-45ASI IDT, Integrated Device Technology Inc, MK2049-45ASI Datasheet - Page 5

• Manufacturer Part Number: MK2049-45ASI
• Description: IC CLK PLL COMM 3.3V 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Synthesizerr

Specifications of MK2049-45ASI

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 49.152MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 49.152MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Charge Pump Current Table
Special considerations must be made in choosing loop
components C
found on our web site.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20 . (The
optional series termination resistor is not shown in the
External Component Schematic.)
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK2049-45A must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
MK2049-45A should use one common connection to the
PCB power plane as shown in the diagram on the next page.
The ferrite bead and bulk capacitor help reduce lower
frequency noise in the supply that can lead to output clock
phase modulation.
IDT™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
MK2049-45A
3.3 VOLT COMMUNICATIONS CLOCK PLL
13.02
R
(k
100
150
200
15
16
18
20
22
24
27
36
47
56
75
SET
S
and C
Charge Pump Current
(I
P
. These recommendations can be
CP
139
125
119
109
100
93
86
68
56
43
35
28
22
15
12
) ( A)
5
Recommended Power Supply Connection for
Optimal Device Performance
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground,
shown as C
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device.
Please refer to MAN05 for the procedure to determine
capacitor values.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed. Please
also refer to the Recommended PCB Layout drawing on
Page 7.
1) Each 0.01 µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No via’s should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The loop filter components must also be placed close to
the CHGP and VIN pins. C
Coupling of noise from other system signal traces should be
Bulk Decoupling Capacitor
Connection to 3.3V
(such as 1 µF Tantalum)
L
Power Plane
in the External Component Schematic. These
0.01 µF Decoupling Capacitors
P
should be closest to the device.
Ferrite
Bead
VCXO AND SYNTHESIZER
MK2049-45A
VDD Pin
VDD Pin
VDD Pin
REV C 051310