SI5367B-B-GQ Silicon Laboratories Inc, SI5367B-B-GQ Datasheet

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SI5367B-B-GQ

Manufacturer Part Number
SI5367B-B-GQ
Description
IC UP-PROG CLK MULTIPLR 100TQFP
Manufacturer
Silicon Laboratories Inc
Type
Clock Multiplierr
Datasheets

Specifications of SI5367B-B-GQ

Package / Case
100-TQFP, 100-VQFP
Pll
Yes with Bypass
Input
Clock
Output
CML, CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
4:5
Differential - Input:output
Yes/Yes
Frequency - Max
808MHz
Divider/multiplier
No/Yes
Voltage - Supply
1.62 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
808MHz
Mounting Style
SMD/SMT
Number Of Outputs
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5367B-B-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
µP-P
Description
The Si5367 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs ranging
from 10 to 707 MHz and generates five frequency-multiplied
clock outputs ranging from 10 to 945 MHz and select
frequencies to 1.4 GHz. The device provides virtually any
frequency translation combination across this operating
range. The outputs are divided down separately from a
common source. The Si5367 input clock frequency and clock
multiplication ratio are programmable through an I
interface. The Si5367 is based on Silicon Laboratories' 3rd-
generation DSPLL
frequency synthesis in a highly integrated PLL solution that
eliminates the need for external VCXO and loop filter
components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at
the application level. Operating from a single 1.8 or 2.5 V
supply, the Si5367 is ideal for providing clock multiplication in
high performance timing applications.
Applications
Preliminary Rev. 0.3 3/07
Device Interrupt
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Clock Select
LOS Alarms
I
2
C/SPI Port
CKIN1
CKIN2
CKIN3
CKIN4
R O G R A M M A B L E
®
technology, which provides any-rate
÷ N31
÷ N32
÷ N33
÷ N34
Control
Copyright © 2007 by Silicon Laboratories
P
2
R E C I S I O N
C or SPI
DSPLL
÷ N2
Features
®
Generates any frequency from 10 to 945 MHz and
select frequencies to 1.4 GHz from an input
frequency of 10 to 710 MHz
Low jitter clock outputs w/jitter generation as low as
0.6 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(30 kHz to 1.3 MHz)
Four clock inputs w/manual or automatically
controlled hitless switching
Five clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 FEC ratios (255/238,
255/237, 255/236)
LOS alarm outputs
Digitally-controlled output phase adjust
I
On-chip voltage regulator for 1.8 or 2.5 V ±10%
operation
Small size: 14 x 14 mm 100-pin TQFP
Pb-free, RoHS compliant
2
C or SPI programmable settings
C
L O C K
P
R E L I M I N A R Y
÷ NC5
÷ NC3
÷ NC4
÷ NC2
÷ NC1
M
U L T I P L I E R
Si5367
D
A TA
VDD (1.8 or 2.5 V)
GND
CKOUT2
CKOUT3
CKOUT4
CKOUT5
CKOUT1
S
H E E T
Si5367

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SI5367B-B-GQ Summary of contents

Page 1

Description The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5367 accepts four clock inputs ranging from 10 to ...

Page 2

Si5367 Table 1. Performance Specifications (V = 1.8 or 2.5 V ±10 – º Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, ...

Page 3

Table 1. Performance Specifications (Continued 1.8 or 2.5 V ±10 – º Parameter Symbol Rise/Fall Time CKO TRF Duty Cycle CKO DC PLL Performance Jitter Generation J GEN Jitter Transfer J PK ...

Page 4

Si5367 0 -20 -40 -60 -80 -100 -120 -140 -160 100 1000 4 155.52 MHz in, 622.08 MHz out 10000 100000 1000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot Preliminary Rev. 0.3 10000000 100000000 ...

Page 5

System Power Supply 130 Ω 130 Ω CKIN1+ CKIN1– 82 Ω 82 Ω Input Clock Sources 3 130 Ω 130 Ω CKIN4+ CKIN4– 82 Ω 82 Ω Control Mode (L) CMODE ...

Page 6

Si5367 1. Functional Description The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequency-multiplied clock outputs ranging ...

Page 7

Pin Descriptions: Si5367 100 RST NC 4 VDD 5 6 VDD GND 7 GND 8 C1B 9 10 C2B C3B 11 INT_ALM 12 CS0_C3A 13 GND 14 15 VDD GND 16 17 ...

Page 8

Si5367 Table 3. Si5367 Pin Descriptions (Continued) Pin # Pin Name 5, 6, 15, 27, 32 42, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 7, 8, 14, 16, 18, GND 19, 21, ...

Page 9

Table 3. Si5367 Pin Descriptions (Continued) Pin # Pin Name 12 INT_ALM 13 CS0_C3A 57 CS1_C4A 29 CKIN4+ 30 CKIN4– 34 CKIN2+ 35 CKIN2– Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. I/O ...

Page 10

Si5367 Table 3. Si5367 Pin Descriptions (Continued) Pin # Pin Name 39 CKIN3+ 40 CKIN3– 44 CKIN1+ 45 CKIN1– 58 C1A 59 C2A 60 SCL 61 SDA_SDO A2_SS Note: Internal register names are indicated by ...

Page 11

Table 3. Si5367 Pin Descriptions (Continued) Pin # Pin Name 71 SDI 77 CKOUT3+ 78 CKOUT3– 82 CKOUT1– 83 CKOUT1+ 87 CKOUT5– 88 CKOUT5+ 90 CMODE 92 CKOUT2+ 93 CKOUT2– 97 CKOUT4– 98 CKOUT4+ GND PAD GND PAD Note: Internal ...

Page 12

... Si5367 3. Ordering Guide Ordering Part Output Clock Number Frequency Range Si5367A-B-GQ 10–945 MHz 970–1134 MHz 1.213–1.417 GHz Si5367B-B-GQ 10–808 MHz Si5367C-B-GQ 10–346 MHz 12 Package 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP Preliminary Rev. 0.3 Temperature Range – °C – °C ...

Page 13

Package Outline: 100-Pin TQFP Figure 4 illustrates the package details for the Si5367. Table 4 lists the values for the dimensions shown in the illustration. Figure 4. 100-Pin Thin Quad Flat Package (TQFP) Table 4. Dimension Min Nom A ...

Page 14

Si5367 5. Recommended PCB Layout 14 Figure 5. PCB Land Pattern Diagram Preliminary Rev. 0.3 ...

Page 15

Table 5. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ...

Page 16

Si5367 OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 3. Updated “2. Pin Descriptions: Si5367”. Changed FSOUT (pins 87 and 88) to CLKOUT5. Changed FS_ALIGN ...

Page 17

N : OTES Preliminary Rev. 0.3 Si5367 17 ...

Page 18

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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