www.ti.com
FEATURES
Choice of Three Phase Comparators
– Exclusive OR
– Edge-Triggered J-K Flip-Flop
– Edge-Triggered RS Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and
for Low Standby Power Consumption
Optimized Power-Supply Voltage Range From
3 V to 5.5 V
Wide Operating Temperature Range . . . –40 C
to 125 C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
DESCRIPTION/ORDERING INFORMATION
The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the
CD74HC4046. The device is specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO)
and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common
to each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input
amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear operational amplifier techniques.
T
PACKAGE
A
Tube of 50
SOP – NS
Reel of 2000
Tube of 40
SOIC – D
–40 C to 125 C
Reel of 2500
Tube of 90
TSSOP – PW
Reel of 2000
TVSOP – DGV
Reel of 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP
SCES656C – FEBRUARY 2006 – REVISED APRIL 2007
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D, DGV, NS, OR PW PACKAGE
PCP
PC1
COMP
VCO
GND
(1)
ORDERING INFORMATION
ORDERABLE PART NUMBER
SN74LV4046ANS
SN74LV4046ANSR
SN74LV4046AD
SN74LV4046ADR
SN74LV4046APW
SN74LV4046APWR
SN74LV4046ADGVR
Copyright © 2006–2007, Texas Instruments Incorporated
SN74LV4046A
WITH VCO
(TOP VIEW)
V
1
16
CC
OUT
PC3
2
15
OUT
OUT
SIG
3
14
IN
IN
PC2
4
13
OUT
OUT
R
INH
5
12
2
C1
6
11
R
A
1
C1
7
10
DEM
B
OUT
8
9
VCO
IN
TOP-SIDE MARKING
74LV4046A
LV4046A
LW046A
LW046A