MC100EP139DWG ON Semiconductor, MC100EP139DWG Datasheet

MC100EP139DWG

Manufacturer Part Number

MC100EP139DWG

Description

IC CLK GEN ECL 2/4 4/5/6 20SOIC

Manufacturer

ON Semiconductor

Series

100EPr

Type

Clock Generatorr

Datasheet

1.MC100EP139DTR2G.pdf (14 pages)

Specifications of MC100EP139DWG

Pll

Input

CML, NECL, PECL

Output

ECL

Number Of Circuits

Ratio - Input:output

1:4

Differential - Input:output

Yes/Yes

Frequency - Max

1GHz

Divider/multiplier

Yes/No

Voltage - Supply

±3 V ~ 5.5 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-SOIC (7.5mm Width)

Frequency-max

1GHz

Mounting Style

SMD/SMT

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

MC100EP139DWGOS

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

MC100EP139DWG

Manufacturer:

ON Semiconductor

Quantity:

135

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

MC100EP139DWG

Manufacturer:

ON Semiconductor

Quantity:

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Download datasheet (182Kb)

MC10EP139, MC100EP139

3.3V / 5V ECL ÷2/4, ÷4/5/6

Clock Generation Chip

Description

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned.

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen with

an asynchronous control. The internal enable flip−flop is clocked on the

falling edge of the input clock, therefore, all associated specification

limits are referenced to the negative edge of the clock input.

therefore the master reset (MR) input may require assertion to ensure

system synchronization. Internal divider design ensures synchronization

between the ÷2/4 and the ÷4/5/6 outputs within a device. All V

proper operation.

device only. For single−ended input conditions, the unused differential

input is connected to V

rebias AC coupled inputs. When used, decouple V

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When

not used, VBB should be left open.

Features

•

November, 2008 − Rev. 11

The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip

The common enable (EN) is synchronous so that the internal dividers

Upon start−up, the internal flip−flops will attain a random state;

The V

The 100 Series contains temperature compensation.

with V

Maximum Frequency > 1.0 GHz Typical

50 ps Output−to−Output Skew

PECL Mode Operating Range: V

NECL Mode Operating Range: V

Open Input Default State

Safety Clamp on Inputs

Synchronous Enable/Disable

Master Reset for Synchronization of Multiple Chips

Pb−Free Packages are Available

pins must be externally connected to power supply to guarantee

Output

Pin, an internally generated voltage supply, is available to this

= −3.0 V to −5.5 V

= 0 V

as a switching reference voltage. V

= 3.0 V to 5.5 V

= 0 V

and V

may also

via a

and

See detailed ordering and shipping information in the package

dimensions section on page 11 of this data sheet.

*For additional marking information, refer to

DW SUFFIX

CASE 948E

CASE 751D

MN SUFFIX

CASE 485E

Application Note AND8002/D.

TSSOP−20

DT SUFFIX

(Note: Microdot may be in either location)

SOIC−20

QFN−20

ORDERING INFORMATION

HEP

KEP

XXX

L,WL

Y, YY

W, WW = Work Week

G or G

http://onsemi.com

= MC10EP

= MC100EP

= 10 or 100

= Assembly Location

= Wafer Lot

= Year

= Pb−Free Package

Publication Order Number:

DIAGRAMS*

HEP or KEP

MARKING

MCXXXEP139

ALYWG

AWLYYWWG

ALYWG

EP139

139

XXXX

MC10EP139/D

Related parts for MC100EP139DWG

MC100EP139DWG Summary of contents

Page 1

MC10EP139, MC100EP139 3.3V / 5V ECL ÷2/4, ÷4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the ...

Page 2

DIVSELb0 3 CLK 4 CLK 5 MC10/100EP139 DIVSELb1 9 DIVSELa 10 Warning: All V and V pins must be externally connected Power Supply ...

Page 3

DIVSELa CLK CLK EN MR DIVSELb0 DIVSELb1 V EE Table 2. FUNCTION TABLES Z = Low−to−High Transition ZZ = High−to−Low Transition DIVSELa DIVSELb0 CLK Q (÷2) Q (÷4) Q (÷5) Q (÷6) Figure 4. CLK and OUTPUT Timing Diagram CLK ...

Page 4

Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...

Page 5

Table 5. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 6

Table 7. 10EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 7

Table 9. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 15 Output LOW Voltage (Note 15 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 8

Table 11. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency max (See Figures and 9 F /JITTER) max t , Propagation Delay CLK, Q (Diff) PLH t PHL t Reset Recovery RR t Setup Time s DIVSEL, ...

Page 9

900 800 700 600 500 400 300 200 (JITTER) 100 É É É É É É É É É É É É É É É É É É É É 0 É É É É É É É É É ...

Page 10

900 800 700 600 500 400 300 200 (JITTER) 100 É É É É É É É É É É É É É É É É É É É É 0 É É É É É É É É É ...

Page 11

... MC10EP139DWR2G MC10EP139MNG MC10EP139MNTXG MC100EP139DT MC100EP139DTG MC100EP139DTR2 MC100EP139DTR2G MC100EP139DW MC100EP139DWG MC100EP139DWR2 MC100EP139DWR2G MC100EP139MNG MC100EP139MNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. Resource Reference of Application Notes ...

Page 12

... −V− 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE Í Í Í Í ...

Page 13

20X T 0. 18X A1 T PACKAGE DIMENSIONS SOIC−20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D−05 ISSUE G q SEATING PLANE C http://onsemi.com 13 ...

Page 14

... Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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