MC100LVEP34DG ON Semiconductor, MC100LVEP34DG Datasheet

IC CLOCK GEN ECL 2/4/8 16SOIC

MC100LVEP34DG

Manufacturer Part Number
MC100LVEP34DG
Description
IC CLOCK GEN ECL 2/4/8 16SOIC
Manufacturer
ON Semiconductor
Series
100LVEPr
Type
Clock Generatorr
Datasheet

Specifications of MC100LVEP34DG

Pll
No
Input
CML, LVDS, NECL, PECL
Output
ECL
Number Of Circuits
1
Ratio - Input:output
1:3
Differential - Input:output
Yes/Yes
Frequency - Max
2.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
±2.375 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
2.8GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC100LVEP34DGOS
MC100LVEP34
2.5V / 3.3V ECL ÷2, ÷4, ÷8
Clock Generation Chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The V
generated voltage supply, is available to this device only. For
single- ended input conditions, the unused differential input is
connected to V
rebias AC coupled inputs. When used, decouple V
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple LVEP34s in a system. Single-ended CLK
input operation is limited to a V
-3.0 V in NECL mode.
Features
© Semiconductor Components Industries, LLC, 2007
June, 2007 - Rev. 10
The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip
The common enable (EN) is synchronous so that the internal
Upon start-up, the internal flip-flops will attain a random state; the
with V
with V
35 ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
The 100 Series Contains Temperature Compensation.
PECL Mode Operating Range: V
NECL Mode Operating Range: V
Open Input Default State
LVDS Input Compatible
Pb-Free Packages are Available
EE
EE
= 0 V
= -2.375 V to -3.8 V
BB
BB
as a switching reference voltage. V
should be left open.
CC
≥ 3.0 V in PECL mode, or V
CC
CC
= 2.375 V to 3.8 V
= 0 V
BB
BB
pin, an internally
and V
BB
may also
1
CC
via a
EE
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
16
16
*For additional marking information, refer to
(Note: Microdot may be in either location)
Application Note AND8002/D.
CASE 751B
D SUFFIX
CASE 948F
TSSOP-16
DT SUFFIX
SO-16
ORDERING INFORMATION
1
A
L, WL
Y
W, WW = Work Week
G or G
http://onsemi.com
1
= Assembly Location
= Wafer Lot
= Year
= Pb-Free Package
Publication Order Number:
16
1
DIAGRAMS*
100LVEP34G
16
MARKING
AWLYWW
1
MC100LVEP34/D
ALYWG
VP34
100
G

Related parts for MC100LVEP34DG

MC100LVEP34DG Summary of contents

Page 1

MC100LVEP34 2.5V / 3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the ...

Page 2

Warning: All V to Power Supply to guarantee proper operation. Figure 1. 16-Lead Pinout (Top View) and Logic Diagram Table 1. PIN ...

Page 3

Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity ...

Page 4

Table 5. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single-Ended) IH (Note 4) V Input LOW Voltage (Single-Ended) ...

Page 5

Table 6. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single-Ended Input LOW Voltage (Single-Ended ...

Page 6

Table 8. AC CHARACTERISTICS V Symbol Characteristic f Maximum Toggle Frequency max (See Figure max t Propagation PLH t Delay to Output PHL t RMS Clock Jitter JITTER (See Figure 4. F /JITTER) max t Setup Time ...

Page 7

There are two distinct functional relationships between the Master Reset and Clock: MR CLK CASE 1: If the MR is de-asserted (H-L), while the Clock is still high, the outputs will follow the second ensuing clock ...

Page 8

... Device Q Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVEP34D MC100LVEP34DG MC100LVEP34DR2 MC100LVEP34DR2G MC100LVEP34DT MC100LVEP34DTG MC100LVEP34DTR2 MC100LVEP34DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...

Page 9

MC100LVEP34 Resource Reference of Application Notes AN1405/D - ECL Clock Distribution Techniques AN1406/D - Designing with PECL (ECL at +5.0 V) AN1503/D - ECLinPSt I/O SPiCE Modeling Kit AN1504/D - Metastability and the ECLinPS Family AN1568/D - Interfacing Between LVDS ...

Page 10

... G K -T- SEATING PLANE 0.25 (0.010 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MC100LVEP34 PACKAGE DIMENSIONS SOIC-16 CASE 751B-05 ISSUE K - 0.25 (0.010 SOLDERING FOOTPRINT* 8X 6.40 1.12 16X 1 16 16X ...

Page 11

... PIN 1 IDENT. 1 0.15 (0.006 -V- C 0.10 (0.004) -T- SEATING D PLANE 16X 0.36 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MC100LVEP34 PACKAGE DIMENSIONS TSSOP-16 CASE 948F-01 ISSUE Ç Ç Ç 9 É ...

Page 12

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT:  Literature Distribution Center for ON Semiconductor  P.O. Box 5163, Denver, Colorado 80217 USA  Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada  Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada   ...

Related keywords