IC PLL FREQ SYNTHESIZER 20-LFCSP

 

ADF4213BCP

Manufacturer Part NumberADF4213BCP
DescriptionIC PLL FREQ SYNTHESIZER 20-LFCSP
ManufacturerAnalog Devices Inc
TypeClock/Frequency Synthesizer (RF/IF)
ADF4213BCP datasheets

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Specifications of ADF4213BCP

Rohs StatusRoHS non-compliantPllYes
InputCMOSOutputClock
Number Of Circuits1Ratio - Input:output3:1
Differential - Input:outputYes/NoFrequency - Max3GHz
Divider/multiplierNo/NoVoltage - Supply2.7 V ~ 5.5 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case20-LFCSPFrequency-max3GHz
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TEMPERATURE – C
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown below in Figure 2. SW1 and
SW2 are normally-closed switches. SW3 is normally-open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
POWER-DOWN
CONTROL
100k
NC
SW2
REF
IN
NC
BUFFER
SW1
SW3
NO
NC = NO CONNECT
RF/IF INPUT STAGE
The RF/IF input stage is shown in Figure 3. It is followed by a
2-stage limiting amplifier to generate the CML (Current Mode
Logic) clock levels needed for the prescaler.
1.6V
BIAS
GENERATOR
2k
2k
RF
A
IN
RF
B
IN
ADF4210/ADF4211/ADF4212/ADF4213
PRESCALER (P/P + 1)
The dual modulus prescaler (P/P + 1), along with the A and
V
= 3V
DD
B counters, enables the large division ratio, N, to be realized
V
= 5V
P
(N = PB + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF/IF input stage and divides
it down to a manageable frequency for the CMOS A and B
counters in the RF and If sections. The prescaler in both
sections is programmable. It can be set in software to 8/9, 16/17,
32/33, or 64/65. See Tables IV and VI. It is based on a syn-
chronous 4/5 core.
RF/IF A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
60
80
100
feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less, when V
they will work with 250 MHz output from the prescaler. Thus,
with an RF input frequency of 2.5 GHz, a prescaler value of
16/17 is valid, but a value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
pin
IN
f
= Output Frequency of external voltage controlled
VCO
oscillator (VCO).
P
= Preset modulus of dual modulus prescaler (8/9,
16/17, etc.).
B
= Preset Divide Ratio of binary 13-bit counter
(3 to 8191).
TO R COUNTER
A
= Preset Divide Ratio of binary 6-bit A counter
(0 to 63).
f
= External reference frequency oscillator.
REFIN
R
= Preset divide ratio of binary 15-bit programmable refer-
ence counter (1 to 32767).
FROM RF
INPUT STAGE
AV
DD
RF/IF COUNTER
The 15-bit RF/IF R counter allows the input reference fre-
AGND
quency to be divided down to product the input clock to the
phase frequency detector (PFD). Division ratios from 1 to
32767 are allowed.
= 5 V. Typically,
DD
= [(P × B) + A] × f
f
/R
VCO
REFIN
N = BP + A
TO PFD
13-BIT B-
COUNTER
LOAD
PRESCALER
P/P + 1
LOAD
5-BIT A-
MODULUS
COUNTER
CONTROL

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