ADF4213BRU-REEL7 | |
|---|---|
| Manufacturer Part Number | ADF4213BRU-REEL7 |
| Description | IC PLL FREQ SYNTHESIZER 20-TSSOP |
| Manufacturer | Analog Devices Inc |
| Type | Clock/Frequency Synthesizer (RF/IF) |
| ADF4213BRU-REEL7 datasheets |
|
| Product Change Notification |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of ADF4213BRU-REEL7 | |||
|---|---|---|---|
| Rohs Status | RoHS non-compliant | Pll | Yes |
| Input | CMOS | Output | Clock |
| Number Of Circuits | 1 | Ratio - Input:output | 3:1 |
| Differential - Input:output | Yes/No | Frequency - Max | 3GHz |
| Divider/multiplier | No/No | Voltage - Supply | 2.7 V ~ 5.5 V |
| Operating Temperature | -40°C ~ 85°C | Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP | Frequency-max | 3GHz |
PrevNext
ADF4210/ADF4211/ADF4212/ADF4213
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
The PFD includes a fixed-delay element that sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no deadzone in the PFD transfer function and gives
a consistent reference spur level.
UP
HI
D1
Q1
U1
R DIVIDER
CLR1
DELAY
CLR2
DOWN
HI
D2
Q2
U2
N DIVIDER
R DIVIDER
N DIVIDER
CP OUTPUT
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF421x family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by P3, P4, P11, and P12. See Tables
III and V. Figure 6 shows the MUXOUT section in block dia-
gram form.
IF ANALOG LOCK DETECT
IF R COUNTER OUTPUT
IF N COUNTER OUTPUT
IF/RF ANALOG LOCK DETECT
MUX
CONTROL
RF R COUNTER OUTPUT
RF N COUNTER OUTPUT
RF ANALOG LOCK DETECT
DIGITAL LOCK DETECT
Lock Detect
MUXOUT can be programmed for two types of lock detect:
Digital Lock Detect and Analog Lock Detect. Digital Lock
Detect is active high. It is set high when the phase error on three
consecutive Phase Detector cycles is less than 15 ns. It will stay
set high until a phase error of greater than 25 ns is detected on
any subsequent PD cycle. The N-channel open-drain analog
lock detect should be operated with an external pull-up resistor
of 10 kΩ nominal. When lock has been detected, it is high with
narrow low-going pulses.
V
P
CHARGE
RF/IF INPUT SHIFT REGISTER
PUMP
The ADF421x family digital section includes a 24-bit input shift
register, a 14-bit IF R counter and a 18-bit IF N counter, com-
prising a 6-bit IF A counter and a 12-bit IF B counter. Also
present is a 14-bit RF R counter and an 18-bit RF N counter,
comprising a 6-bit RF A counter and a 12-bit RF B counter.
Data is clocked into the 24-bit shift register on each rising edge
of CLK. The data is clocked in MSB first. Data is transferred
CP
U3
from the shift register to one of four latches on the rising edge of
LE. The destination latch is determined by the state of the two
control bits (C2, C1) in the shift register. These are the two LSBs
DB1, DB0 as shown in the timing diagram of Figure 1. The
truth table for these bits is shown in Table VI. Table I shows a
summary of how the latches are programmed.
CPGND
Control Bits
C2
0
0
1
1
DV
DD
MUXOUT
DGND
Table I. C2, C1 Truth Table
C1
Data Latch
0
IF R Counter
1
IF AB Counter (A and B)
0
RF R Counter
1
RF AB Counter (A and B)
Related parts for ADF4213BRU-REEL7 | |||
|---|---|---|---|
| Part Number | Description | Manufacturer | Datasheet |
 ADF4213BRU |
IC PLL FREQ SYNTHESIZER 20-TSSOP | Analog Devices Inc |
|
 ADF4213BRUZ |
DUAL PLL,2.5/1.1GHz I.C | Analog Devices Inc |
|
|
ADF4213BRU-REEL |
IC PLL FREQ SYNTHESIZER 20-TSSOP | Analog Devices Inc |
|
|
ADF4213BRUZ-REEL |
DUAL PLL,2.5/1.1GHz I.C | Analog Devices Inc |
|
|
ADF4213BRUZ-REEL7 |
DUAL PLL,2.5/1.1GHz I.C | Analog Devices Inc |
|
 ADF4213BCP |
IC PLL FREQ SYNTHESIZER 20-LFCSP | Analog Devices Inc |
|
|
ADF4213BCP-REEL |
IC PLL FREQ SYNTHESIZER 20-LFCSP | Analog Devices Inc |
|
|
ADF4213BCP-REEL7 |
IC PLL FREQ SYNTHESIZER 20-LFCSP | Analog Devices Inc |
|
|
ADF4213BCPZ |
DUAL PLL 2.5/1.1 GHZ | Analog Devices Inc |
|
|
ADF4213BCPZ-RL |
DUAL PLL 2.5/1.1 GHZ | Analog Devices Inc | |
|
ADF4213BCPZ-RL7 |
DUAL PLL 2.5/1.1 GHZ | Analog Devices Inc |
|
 ADXL203EB |
±1.7g Dual-Axis IMEMS Accelerometer Evaluation Board | Analog Devices Inc |
|
 AD558SD883B |
Voltage-output 8-bit digital-to-analog converter, including output amplifier, full microprocessor interface and precision | Analog Devices |
|
|
AD73360 |
6-Channel AFE Processor for General Purpose Applications Including Industrial Power Metering or Multi-Channel Analog Inputs | Analog Devices |
|
|
AD558 |
Voltage-output 8-bit digital-to-analog converter, including output amplifier, full microprocessor interface and precision | Analog Devices |
|
