CY24212SXC-5T Cypress Semiconductor Corp, CY24212SXC-5T Datasheet

IC CLOCK GEN MPEG W/VCXO 8SOIC

CY24212SXC-5T

Manufacturer Part Number
CY24212SXC-5T
Description
IC CLOCK GEN MPEG W/VCXO 8SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Clock Generator, Fanout Distributionr
Series
MediaClock™r
Datasheet

Specifications of CY24212SXC-5T

Number Of Circuits
1
Package / Case
8-SOIC (3.9mm Width)
Pll
Yes
Input
Clock
Output
Clock
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
27.027MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
27.027MHz
Maximum Input Frequency
27 MHz
Minimum Input Frequency
13.5 MHz
Output Frequency Range
27 MHz to 27.027 MHz
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
Table 1. CY24212 (-1, -2) Frequency Select Option
Table 2. CY24212 (-3, -5) Frequency Select Option
Cypress Semiconductor Corporation
Document #: 38-07402 Rev. *D
Part Number
Integrated phase-locked loop (PLL)
Low jitter, high-accuracy outputs
VCXO with analog adjust
3.3V operation
CY24212-1
CY24212-2
CY24212-3
CY24212-5
Logic Block Diagram
FSEL
FSEL
0
1
0
1
Outputs
1
2
2
2
13.5 MHz/27 MHz (selectable)
13.5 MHz/27 MHz (selectable)
XOUT
VCXO
FSEL
XIN
Reference
Reference
Input Frequency Range
13.5 MHz
27 MHz
27 MHz
27 MHz
OSC
27 MHz
27 MHz
PRELIMINARY
198 Champion Court
Q
CLKA/CLKB
Φ
MPEG Clock Generator with VCXO
27 MHz
27 MHz
27 MHz
27 MHz
CLKA
P
27 MHz
Two copies of 27 MHz
27 MHz/27.027 MHz (-1 ppm)
27 MHz/27.027 MHz (0 ppm)
PLL
VCO
Benefits
VDD
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Enables application compatibility
VSS
San Jose
27.027 MHz
Output Frequencies
27 MHz
CLKB
DIVIDERS
OUTPUT
,
CA 95134-1709
MediaClock™
CLKA (27 MHz)
27 MHz (-2)
27/27.027 MHz (-3)
Revised April 25, 2008
CY24212
408-943-2600
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Related parts for CY24212SXC-5T

CY24212SXC-5T Summary of contents

Page 1

... MHz Table 2. CY24212 (-3, -5) Frequency Select Option FSEL Reference 0 27 MHz 1 27 MHz Cypress Semiconductor Corporation Document #: 38-07402 Rev. *D PRELIMINARY MPEG Clock Generator with VCXO Benefits ■ Highest-performance PLL tailored for multimedia applications ■ Meets critical timing requirements in complex system designs ■ ...

Page 2

Pin Configurations CY24212-1 1 XOUT 8 XIN 7 2 VSS VDD 3 6 VCXO FSEL 5 4 CLKA 27 MHz VSS Table 3. Pin Definition Name Pin Number Description XIN 1 Reference Input. VDD 2 Voltage Supply. VCXO 3 Input ...

Page 3

DC Electrical Specifications Parameter Name I Output High Current OH I Output Low Current OL C Input Capacitance IN I Input High Current IH I Input Low Current IL f VCXO Pullability Range ΔXO V VCXO Input Range VCXO I ...

Page 4

... CY24212SC-1 S8 [4] CY24212SC-1T S8 CY24212SC-2 [4] S8 [4] CY24212SC-2T S8 [4] CY24212SC-3 S8 CY24212SC-3T [4] S8 CY24212SC-5 [4] S8 [4] CY24212SC-5T S8 Pb-free CY24212SXC-5 [4] S8 CY24212SXC-5T [4] S8 CY24212KSXC-5 S8 Note 4. Not recommended for new designs. Document #: 38-07402 Rev. *D PRELIMINARY Figure 2. Duty Cycle Definition / Package Type Operating Range 8-Pin SOIC ...

Page 5

Package Drawing and Dimensions 0.189[4.800] 0.196[4.978] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] Document #: 38-07402 Rev. *D PRELIMINARY 8-lead (150-Mil) SOIC S8 Figure 4. PIN DIMENSIONS IN INCHES[MM] MIN. 2. PIN OPTIONAL, ...

Page 6

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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