MC145151DW2

Manufacturer Part NumberMC145151DW2
DescriptionIC PAR-IN PLL FREQ SYNTH 28-SOIC
ManufacturerFreescale Semiconductor
TypePLL Clock/Frequency Synthesizer
MC145151DW2 datasheets

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Specifications of MC145151DW2

PllYesInputClock
OutputCMOSNumber Of Circuits1
Ratio - Input:output1:1Differential - Input:outputNo/No
Frequency - Max25MHzDivider/multiplierYes/No
Voltage - Supply3 V ~ 9 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case28-SOIC (7.5mm Width)
Frequency-max25MHzLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
N0 - N11
N Counter Programming Inputs (Pins 11 - 20, 22 - 25)
These inputs provide the data that is preset into the ÷ N counter when it reaches the count of zero. N0 is
the least significant and N13 is the most significant. Pull-up resistors ensure that inputs left open remain
at a logic 1 and require only an SPST switch to alter data to the zero state.
T/R
Transmit/Receive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided at the N inputs. This is normally used for offsetting
the VCO frequency by an amount equal to the IF frequency of the transceiver. This offset is fixed at 856
when T/R is low and gives no offset when T/R is high. A pull-up resistor ensures that no connection will
appear as a logic 1 causing no offset addition.
OSC
, OSC
in
out
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on-chip reference oscillator when connected to terminals of an external parallel
resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC
ground and OSC
to ground. OSC
out
signal. This signal is typically ac coupled to OSC
levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC
1.2.2
Output Pins
PD
out
Phase Detector A Output (Pin 4)
Three-state output of phase detector for use as loop-error signal. Double-ended outputs are also available
for this purpose (see φ
and φ
V
R
Frequency f
> f
or f
Leading: Negative Pulses
V
R
V
Frequency f
< f
or f
Lagging: Positive Pulses
V
R
V
Frequency f
= f
and Phase Coincidence: High-Impedance State
V
R
φ
, φ
R
V
Phase Detector B Outputs (Pins 8, 9)
These phase detector outputs can be combined externally for a loop-error signal. A single-ended output is
also available for this purpose (see PD
If frequency f
is greater than f
V
pulsing low. φ
remains essentially high.
R
If the frequency f
is less than f
V
pulsing low. φ
remains essentially high.
V
and both are in phase, then both φ
If the frequency of f
= f
V
R
minimum time period when both pulse low in phase.
MC145151-2 and MC145152-2 Technical Data, Rev. 5
4
may also serve as the input for an externally-generated reference
in
, but for larger amplitude signals (standard CMOS logic
in
).
).
out
is leading, then error information is provided by φ
or if the phase of f
R
V
is lagging, then error information is provided by φ
or if the phase of f
R
V
V
and φ
remain high except for a small
R
Freescale Semiconductor
to
in
.
out
V
R

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