MC145151DW2

Manufacturer Part NumberMC145151DW2
DescriptionIC PAR-IN PLL FREQ SYNTH 28-SOIC
ManufacturerFreescale Semiconductor
TypePLL Clock/Frequency Synthesizer
MC145151DW2 datasheets

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Specifications of MC145151DW2

PllYesInputClock
OutputCMOSNumber Of Circuits1
Ratio - Input:output1:1Differential - Input:outputNo/No
Frequency - Max25MHzDivider/multiplierYes/No
Voltage - Supply3 V ~ 9 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case28-SOIC (7.5mm Width)
Frequency-max25MHzLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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N0 - N9
N Counter Programming Inputs (Pins 11 - 20)
The N inputs provide the data that is preset into the ÷ N counter when it reaches the count of 0. N0 is the
least significant digit and N9 is the most significant. Pull-up resistors ensure that inputs left open remain
at a logic 1 and require only a SPST switch to alter data to the zero state.
A0 - A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of f
Section 4.3, “Dual-Modulus
Prescaling,”
ensure that inputs left open will remain at a logic 1.
OSC
, OSC
in
out
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on-chip reference oscillator when connected to terminals of an external parallel
resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC
ground and OSC
to ground. OSC
out
signal. This signal is typically ac coupled to OSC
levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC
2.2.2
Output Pins
φ
, φ
R
V
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally for a loop-error signal.
If the frequency f
is greater than f
V
φ
pulsing low. φ
remains essentially high.
V
R
If the frequency f
is less than f
V
pulsing low. φ
remains essentially high.
V
and both are in phase, then both φ
If the frequency of f
= f
V
R
minimum time period when both pulse low in phase.
MC
Dual-Modulus Prescale Control Output (Pin 9)
Signal generated by the on-chip control logic circuitry for controlling an external dual-modulus prescaler.
The MC level will be low at the beginning of a count cycle and will remain low until the ÷ A counter has
counted down from its programmed value. At this time, MC goes high and remains high until the ÷ N
counter has counted the rest of the way down from its programmed value (N - A additional counts since
both ÷ N and ÷ A are counting down during the first portion of the cycle). MC is then set back low, the
counters preset to their respective programmed values, and the above sequence repeated. This provides for
a total programmable divide value (N
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
that require a logic 0 on the MC output (see
in
on page
21). The A inputs all have internal pull-up resistors that
may also serve as the input for an externally-generated reference
in
, but for larger amplitude signals (standard CMOS logic
in
or if the phase of f
is leading, then error information is provided by
R
V
is lagging, then error information is provided by φ
or if the phase of f
R
V
V
) = N • P + A where P and P + 1 represent the dual-modulus prescaler
T
and φ
remain high except for a small
R
to
in
.
out
R
9

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