SI4136-BM Silicon Laboratories Inc, SI4136-BM Datasheet
SI4136-BM
Specifications of SI4136-BM
Related parts for SI4136-BM
SI4136-BM Summary of contents
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... GND GND IFLB 6 19 IFLA GND GND 8 17 VDDD GND 9 16 GND GND 10 15 XIN GND 11 14 RFOUT PWDN 12 13 VDDR AUXOUT Si4136- GND GND 2 20 GND IFLB IFLA GND 4 18 GND GND VDDD 6 16 GND GND 7 15 GND XIN Patents pending ...
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... Si4136/Si4126 2 Rev. 1.2 ...
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... RF and IF Outputs (RFOUT and IFOUT Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Powerdown Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Auxiliary Output (AUXOUT Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Descriptions: Si4136- Pin Descriptions: Si4136- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Si4136 Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Outline: Si4136- Package Outline: Si4136- Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Si4136/Si4126 Rev. 1.2 Page 3 ...
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... Si4136/Si4126 Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. ...
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... For signals SCLK, SDATA, SEN, and PWDN. 3. For signal AUXOUT. Symbol Test Condition RF1 and IF operating PWDN = –500 µ 500 µ Rev. 1.2 Si4136/Si4126 Min Typ Max Unit — 25 — 15 — — — 1 — µA 0.7 V — — — — 0 –10 — 10 µA –10 — ...
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... Si4136/Si4126 Table 4. Serial Interface Timing (V = 2 – ° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time 2 SDATA Setup Time to SCLK↑ 2 SDATA Hold Time from SCLK↑ 2 SEN↓ to SCLK↑ Delay Time 2 SCLK↑ ...
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... Figure 2. Serial Interface Timing Diagram First bit clocked data field Figure 3. Serial Word Format Rev. 1.2 Si4136/Si4126 A A Last bit clocked address field 7 ...
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... Si4136/Si4126 Table 5. RF and IF Synthesizer Characteristics 2 3 – ° Parameter XIN Input Frequency XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency 2 RF1 VCO Tuning Range 2 RF2 VCO Tuning Range IF VCO Center Frequency Range IFOUT Tuning Range from f CEN IFOUT VCO Tuning Range from f ...
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... Offset = 3 MHz 3 t Figures 4, 5 pup f > 500 kHz φ Figures 4, 5 pup ≤ 500 kHz f φ Figures 4, 5 pdn Rev. 1.2 Si4136/Si4126 Min Typ Max Unit — –28 –20 dBc — –23 –20 dBc — –26 –20 dBc –7 –3.5 –0.5 dBm – ...
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... Si4136/Si4126 RF synthesizers settled to within 0.1 ppm frequency error. t pup PWDN SEN PDIB = 1 PDIB = 0 SDATA PDRB = 1 PDRB = 0 Figure 4. Software Power Management Timing Diagram 10 t pdn PWDN PWDN Figure 5. Hardware Power Management Timing Diagram Rev. 1.2 RF synthesizers settled to within 0.1 ppm frequency error. ...
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... Figure 6. Typical Transient Response RF1 at 2.4 GHz with 1 MHz Phase Detector Update Frequency Rev. 1.2 Si4136/Si4126 11 ...
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... Si4136/Si4126 -60 -70 -80 -90 -100 -110 -120 -130 -140 1.E+02 Figure 7. Typical RF1 Phase Noise at 2.4 GHz with 1 MHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 2.4 GHz with 1 MHz Phase Detector Update Frequency 12 1.E+03 1.E+04 Offset Frequency (Hz) Typical RF1 Phase Noise at 2.4 GHz Rev ...
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... Figure 9. Typical RF2 Phase Noise at 2.1 GHz with 1 MHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 2.1 GHz with 1 MHz Phase Detector Update Frequency 1.E+04 1.E+05 Offset Frequency (Hz) Typical RF2 Phase Noise at 2.1 GHz Rev. 1.2 Si4136/Si4126 1.E+06 13 ...
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... Si4136/Si4126 -60 -70 -80 -90 -100 -110 -120 -130 -140 1.E+02 Figure 11. Typical IF Phase Noise at 800 MHz with 1 MHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 800 MHz with 1 MHz Phase Detector Update Frequency 14 1.E+03 1.E+04 Offset Frequency (Hz) Typical IF Phase Noise at 800 MHz Rev ...
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... NC 6 GND GND 9 GND 10 GND 560 pF 11 RFOUT RFOUT V 0.022 µ VDDR *Add 30 Ω series resistor if using IF output divide values and f Figure 13. Typical Application Circuit: Si4136-BT Si4136/Si4126 V DD Si4136 30 Ω ∗ 24 SEN 0.022 µF 23 VDDI 22 IFOUT 21 GND 20 IFLB 19 IFLA 18 GND V 0.022 µF ...
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... MHz, the Si4136 includes a programmable divide-by-2 Register 0, D6) on the XIN input. By enabling this option, the Si4136 can accept a range of TCXO frequencies from 25 MHz to 50 MHz. This feature makes the Si4136 ideal for W-LAN radio designs operating at an XIN of 44 MHz. ...
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... Si4136 will correct for the variation with the self-tuning algorithm. For more information on designing the external trace inductor, please refer to Application Note 31. Self-Tuning Algorithm ). The IF VCO has a ...
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... Divider register was last written. For example, programming automatically selects the RF1 VCO output. Figure 13 on page 15 shows an application diagram for the Si4136. The RF output signal must be AC coupled 1 to its load through a capacitor. The IFOUT pin must also be AC coupled to its load 1/2 through a capacitor ...
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... When the PWDN pin is high, power management is under control of the Powerdown register bits. The IF and RF sections of the Si4136 circuitry can be individually powered down by setting the Powerdown register bits PDIB and PDRB low. The reference frequency amplifier will also be powered up if either the PDRB and PDIB bits are high ...
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... Si4136/Si4126 PWDN Pin AUTOPDB PWDN = 0 PWDN = 1 Note don’t care. 20 Table 10. Powerdown Configuration PDIB PDRB IF Circuitry Rev. 1.2 RF Circuitry OFF OFF OFF OFF OFF ON ON OFF ...
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... Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior. Table 11. Register Summary Bit Bit Bit Bit Bit Bit Bit Bit AUXSEL IFDIV RF1 N RF2 Rev. 1.2 Si4136/Si4126 Bit Bit Bit Bit Bit Bit XIN LPWR AUTO PDB DIV2 PDIB IF R RF1 R RF2 R IF Bit PDRB 21 ...
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... Si4136/Si4126 Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name AUXSEL Bit Name 17:14 Reserved 13:12 AUXSEL 11:10 IFDIV 9:7 Reserved 6 XINDIV2 5 LPWR 4 Reserved 3 AUTOPDB 2:0 Reserved IFDIV XIN DIV2 Function Program to zero. ...
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... IF Phase Detector Gain Constant. N Value K PI <2048 = 00 2048–4095 = 01 4096–8191 = 10 >8191 = 11 RF2 Phase Detector Gain Constant. N Value K P2 <2048 = 00 2048–4095 = 01 4096–8191 = 10 >8191 = 11 RF1 Phase Detector Gain Constant. N Value K P1 <4096 = 00 4096–8191 = 01 8192–16383 = 10 >16383 = 11 Rev. 1.2 Si4136/Si4126 ...
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... Si4136/Si4126 Register 2. Powerdown Address Field (A[3:0]) = 0010 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:2 Reserved 1 PDIB 0 PDRB Register 3. RF1 N Divider Address Field (A[3:0]) = 0011 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit ...
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... Program to zero. 12 Divider for RF2 Synthesizer. RF2 R RF2 Program to zero. N Divider for IF Synthesizer. ≥ 56 Function can be any value from 7 to 8189 8189 8189 8189 Function can be any value from 7 to 8189 8189 8189 8189 if K Rev. 1.2 Si4136/Si4126 Function RF1 = RF2 = 00 ...
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... Si4136/Si4126 Register Divider Address Field (A[3:0]) = 1000 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:13 Reserved Program to zero. 12 Divider for IF Synthesizer Function can be any value from 7 to 8189 8189 8189 8189 if K Rev. 1 ...
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... Pin Descriptions: Si4136-BT Pin Number(s) Name Description 1 SCLK Serial clock input 2 SDATA Serial data input 8–10, GND Common ground 16, 18 connect 11 RFOUT Radio frequency (RF) output of the selected RF VCO 12 VDDR Supply voltage for the RF analog circuitry 13 AUXOUT Auxiliary output 14 PWDN Powerdown input pin ...
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... Si4136/Si4126 Pin Descriptions: Si4136-BM Pin Number(s) Name 7–9, 14, GND 16, 18, 21, 22 RFOUT 11 VDDR 12 AUXOUT 13 PWDN 15 XIN 17 VDDD 19, 20 IFLA, IFLB 23 IFOUT 24 VDDI 25 SEN 26 SCLK 27 SDATA GND GND 2 20 GND IFLB IFLA GND 4 18 GND GND VDDD 6 16 GND GND 7 15 GND ...
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... Ordering Guide Ordering Part Number Si4136-BT Si4136-BM Si4126-BM Si4136 Derivative Devices The Si4136 performs both IF and dual-band RF frequency synthesis. The Si4126 is a derivative of this device. The Si4126 features two synthesizers, RF2 and IF; it does not include RF1. The pinouts for the Si4126 and the Si4136 are the same ...
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... Si4136/Si4126 Package Outline: Si4136-BT Figure 18 illustrates the package details for the Si4136-BT. Table 12 lists the values for the dimensions shown in the illustration. D γ Figure 18. 24-Pin Thin Shrink Small Outline Package (TSSOP) Table 12. Package Diagram Dimensions Symbol *Note: To guarantee coplanarity ( θ Approximate device weight is 115.7 mg. ...
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... Package Outline: Si4136-BM Figure 19 illustrates the package details for the Si4136-BM. Table 13 lists the values for the dimensions shown in the illustration D TOP VIEW FOR ODD TERMINAL/SIDE Figure 19. 28-Pin Micro Leadframe Package (MLP E1/2 E θ SECTION "C–C" SCALE: NONE ...
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... Si4136/Si4126 Document Change List Revision 1.1 to Revision 1.2 TSSOP outline updated. 32 Rev. 1.2 ...
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... Notes: Si4136/Si4126 Rev. 1.2 33 ...
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... Si4136/Si4126 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...