MPC93R51FA Freescale Semiconductor, MPC93R51FA Datasheet

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MPC93R51FA

Manufacturer Part Number
MPC93R51FA
Description
IC PLL CLOCK DRIVER LV 32-LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Driver, Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of MPC93R51FA

Pll
Yes
Input
LVCMOS, LVPECL
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
3:9
Differential - Input:output
Yes/No
Frequency - Max
240MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
240MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Manufacturer
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Part Number:
MPC93R51FA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
Technical Data
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage PLL Clock Driver
high performance clock distribution systems. With output frequencies of up to
240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal
solution for the most demanding clock tree designs. The device offers 9 low skew
clock outputs, each is configurable to support the clocking needs of the various
high-performance microprocessors including the PowerQuicc II integrated
communication microprocessor. The devices employ a fully differential PLL
design to minimize cycle-to-cycle and long-term jitter.
Features
Functional Description
operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback
path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be
selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of
the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs
is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using
the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2
and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input
(TCLK). The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test
mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended
for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification
does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes
the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase
locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is 3.3 V compatible and requires no external
loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the
MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a
7x7 mm
Application Information
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase
offset between the outputs and the reference signal.
Freescale Confidential Proprietary, NDA Required / Preliminary
The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for
The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with
25–240 MHz output frequency range
Fully integrated PLL
Compatible to various microprocessors such as PowerQuicc II
Supports networking, telecommunications and computer applications
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
LVPECL and LVCMOS compatible inputs
External feedback enables zero-delay configurations
Output enable/disable and static test mode (PLL enable/disable)
Low skew characteristics: maximum 150 ps output-to-output
Cycle-to-cycle jitter max. 22 ps RMS
32-lead LQFP package
32-lead Pb-free Package Available
Ambient Temperature Range 0°C to +70°C
Pin & Function Compatible with the MPC951
9 outputs LVCMOS PLL clock generator
2
32-lead LQFP package.
PLL CLOCK GENERATOR
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
LOW VOLTAGE 3.3 V
MPC93R51
Pb-FREE PACKAGE
CASE 873A-03
CASE 873A-03
FA SUFFIX
AC SUFFIX
Rev. 4, 1/2005
MPC93R51

Related parts for MPC93R51FA

MPC93R51FA Summary of contents

Page 1

... This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Confidential Proprietary, NDA Required / Preliminary MPC93R51 Rev. 4, 1/2005 MPC93R51 LOW VOLTAGE 3 ...

Page 2

... PLL 8 ÷ FB 200 – 480 MHz CCA Figure 1. MPC93R51 Logic Diagram MPC93R51 QC0 QC1 1 QD0 QD1 QD2 1 QD3 QD4 . Please see application section for details QD2 15 V CCO 14 QD3 13 GND 12 QD4 11 V CCO PCLK 8 Advanced Clock Drivers Devices Freescale Semiconductor ...

Page 3

... Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Advanced Clock Drivers Devices Freescale Semiconductor Type LVPECL Differential clock reference ...

Page 4

... Alternatively, the device drives up to two 50 Ω series terminated transmission lines. TT Max Unit Condition Per output pF Inputs Max Unit Condition V + 0.3 V LVCMOS CC 0.8 V LVCMOS mV LVPECL V –0.6 V LVPECL CC ( – Ω ±150 µ GND Pin CCA 10 mA All V Pins CC range CMR Advanced Clock Drivers Devices Freescale Semiconductor ...

Page 5

... CMR and the input swing lies within the The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t are within the specified range. Advanced Clock Drivers Devices Freescale Semiconductor (1) = 0° to 70°C) A Min Typ ÷ 4 feedback 50 ÷ ...

Page 6

... CLK relative to the feedback SK(O) QA TCLK 2 x 100 MHz QB REF_SEL QC0 2 x 100 MHz QC1 PLL_EN QD0 FSELA QD1 FSELB 4 x 100 MHz QD2 FSELC QD3 FSELD QD4 Ext_FB MPC93R51 100 MHz (Feedback) (Feedback of QD4) Advanced Clock Drivers Devices Freescale Semiconductor ...

Page 7

... AC characteristic table for V RMS). I/O jitter is frequency dependent with a maximum at Advanced Clock Drivers Devices Freescale Semiconductor the lowest VCO frequency (200 MHz for the MPC93R51). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter ...

Page 8

... Z = 50Ω 36Ω OutA Z = 50Ω 36Ω OutB0 Z = 50Ω 36Ω OutB1 Figure 8 show the simulation results shows a step in the waveform. This ÷ Ω Ω Ω Ω S Ω 3.0 (25 ÷ (18+17+25 1.31 V Advanced Clock Drivers Devices Freescale Semiconductor ...

Page 9

... Generator Z = 50Ω Figure 11. PCLK MPC9R351 AC Test Reference Advanced Clock Drivers Devices Freescale Semiconductor Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the ...

Page 10

... Figure 19. Transition Time Test Reference t (∅) ) Test Reference PD t SK(O) SK( –1/f | JIT(PER Figure 17. Period Jitter V =3 2.4 0. Advanced Clock Drivers Devices Freescale Semiconductor V CC ÷ GND V CC ÷ GND V CC ÷ GND V CC ÷ GND ...

Page 11

... D1 D1/2 PIN 1 INDEX E1 D 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ (S) A1 (L1) DETAIL AD Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS 4X 0. DETAIL G E 32X 0.1 C BASE PLATING METAL 0. SECTION F 0.25 GAUGE PLANE L θ˚ CASE 873A-03 ...

Page 12

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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