DS1020S-15 Maxim Integrated Products, DS1020S-15 Datasheet

DELAY PROG 8-BIT 0.15NS 16-SOIC

DS1020S-15

Manufacturer Part Number
DS1020S-15
Description
DELAY PROG 8-BIT 0.15NS 16-SOIC
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1020S-15

Number Of Taps/steps
256
Function
Programmable
Delay To 1st Tap
10nS
Tap Increment
0.15nS
Available Total Delays
48.25ns
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Independent Delays
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS1020S-15
Manufacturer:
MAXIM/美信
Quantity:
20 000
FEATURES
DESCRIPTION
The DS1020 Programmable 8-Bit Silicon Delay Line consists of an 8-bit, user-programmable CMOS
silicon integrated circuit. Delay values, programmed using either the 3-wire serial port or the 8-bit
parallel port, can be varied over 256 equal steps. The fastest model (-15) offers a maximum delay of
48.25 ns with an incremental delay of 0.15 ns, while the slowest model (-200) has a maximum delay of
520 ns with an incremental delay of 2 ns. All models have an inherent (step-zero) delay of 10 ns. After
the user-determined delay, the input logic state is reproduced at the output without inversion. The
DS1020 is TTL- and CMOS-compatible, capable of driving 10 74LS-type loads, and features both rising
and falling edge accuracy.
The all-CMOS DS1020 integrated circuit has been designed as a reliable, economic alternative to hybrid
programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space-saving
surface mount 16-pin SOIC.
www.dalsemi.com
All-silicon time delay
Models with 0.15 ns, 0.25 ns, 0.5 ns, 1 ns,
and 2 ns steps
Programmable using 3-wire serial port or
8-bit parallel port
Leading and trailing edge accuracy
Standard 16-pin DIP or 16-pin SOIC
Economical
Auto-insertable, low profile
Low-power CMOS
TTL/CMOS-compatible
Vapor phase, IR and wave solderable
1 of 9
Q/PO
GND
DS1020 16-pin DIP (300-mil)
See Mech. Drawings Section
P2
P3
P4
P1
IN
E
PIN ASSIGNMENT
PIN DESCRIPTION
IN
P0-P7
GND
OUT
V
S
E
C
Q
D
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
10
11
9
Programmable 8-Bit
- Delay Input
- Parallel Program Pins
- Ground
- Delay Output
- +5 Volts
- Mode Select
- Enable
- Serial Port Clock
- Serial Data Output
- Serial Data Input
Silicon Delay Line
V
OUT
S
P7
P6
C
P5
D
CC
Q/PO
GND
DS1020S 16-pin SOIC (300-mil)
P2
P3
P4
See Mech. Drawings Section
P1
IN
E
1
2
3
4
5
6
7
8
DS1020
16
15
14
13
12
10
11
9
111799
V
OUT
S
P7
P6
C
P5
D
CC

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DS1020S-15 Summary of contents

Page 1

... Q/ GND GND DS1020 16-pin DIP (300-mil) DS1020S 16-pin SOIC (300-mil) See Mech. Drawings Section PIN DESCRIPTION IN - Delay Input P0-P7 - Parallel Program Pins GND - Ground OUT - Delay Output Volts Mode Select E - Enable C - Serial Port Clock Q - Serial Data Output D - Serial Data Input DS1020 ...

Page 2

PARALLEL MODE (S=1) In the PARALLEL programming mode, the output of the DS1020 will reproduce the logic state of the input after a delay determined by the state of the eight program input pins P0 - P7. The parallel inputs ...

Page 3

FUNCTIONAL BLOCK DIAGRAM Figure 1 SERIAL READOUT Figure ...

Page 4

CASCADING MULTIPLE DEVICES (DAISY CHAIN) Figure 3 PART NUMBER TABLE Table 1 PART STEP ZERO NUMBER DELAY TIME DS1020-15 10 ± 2 DS1020-25 10 ± 2 DS1020-50 10 ± 2 DS1020-100 10 ± 2 DS1020-200 10 ± 3 DELAYS VS. ...

Page 5

DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 4 TEST SETUP DESCRIPTION Figure 4 illustrates the hardware configuration used for measuring the timing parameters of the DS1020. The input waveform is produced by a precision pulse generator under software control. Time delays are ...

Page 6

ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current * This is a stress rating only and functional operation of the device at these or any other conditions above ...

Page 7

PARAMETER SYMBOL Parallel Input Change to Delay Invalid Enable to Delay Valid Enable to Delay Invalid V Valid to Device CC Functional Input Pulse Width Input to Output Delay Input Period CAPACITANCE PARAMETER SYMBOL Input Capacitance TIMING DIAGRAM: SILICON ...

Page 8

TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the t ...

Page 9

... TIMING DIAGRAM: SERIAL MODE ( Figure 8 NOTES: 1. All voltages are referenced to ground and 25°C. Delay accurate on both rising and falling edges within tolerances given in CC Table 1. 3. Measured with output open. 4. The “Q” output will only source 4 mA. This pin is only intended to drive other DS1020s ...

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