DS1005M-100 Maxim Integrated Products, DS1005M-100 Datasheet

DELAY LINE 5TAP 100NS MAX 8-DIP

DS1005M-100

Manufacturer Part Number
DS1005M-100
Description
DELAY LINE 5TAP 100NS MAX 8-DIP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1005M-100

Number Of Taps/steps
5
Function
Tapped
Delay To 1st Tap
20nS
Tap Increment
20nS
Available Total Delays
100ns
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Independent Delays
-
Other names
DS1005M100

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS1005M-100
Manufacturer:
DALLAS
Quantity:
5 510
Part Number:
DS1005M-100
Manufacturer:
ALLE
Quantity:
5 510
Part Number:
DS1005M-100
Manufacturer:
NS/国半
Quantity:
20 000
Company:
Part Number:
DS1005M-100
Quantity:
22
FEATURES
DESCRIPTION
The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns
to 250 ns, with an accuracy of 2 ns or 3%, whichever is greater. This device is offered in a standard 14-
pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin
SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is
achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC
packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead
configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by
the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
meet special needs. For special requests and rapid delivery, call (972) 371–4348.
www.dalsemi.com
All-silicon time delay
5 taps equally spaced
Delay tolerance ±2 ns or ±3%, whichever is
greater
Stable and precise over temperature and
voltage range
Leading and trailing edge accuracy
Economical
Auto-insertable, low profile
Standard 14-pin DIP, 8-pin DIP, or 16-pin
SOIC
Tape and reel available for surface-mount
Low-power CMOS
TTL/CMOS compatible
Vapor phase, IR and wave solderability
Custom delays available
Quick turn prototypes
Extended temperature range available
TAP 2
TAP 4
DS1005 14-Pin DIP (300-mil)
1 of 6
GND
See Mech. Drawings Section
NC
NC
NC
IN
PIN ASSIGNMENT
PIN DESCRIPTION
TAP 1-TAP 5 - TAP Output Number
V
GND
NC
IN
1
2
3
4
5
6
7
CC
5-Tap Silicon Delay Line
TAP 2
TAP 4
DS1005M 8-Pin DIP (300-mil)
13
12
14
11
10
GND
See Mech. Drawings Section
9
8
IN
NC
V
NC
NC
TAP 1
TAP 3
TAP 5
- +5 Volts
- Ground
- No Connection
- Input
CC
1
2
3
4
TAP 2
TAP 4
GND
See Mech. Drawings Section
NC
NC
NC
NC
IN
8
7
6
5
DS1005S 16-Pin SOIC
V
TAP 1
TAP 3
TAP 5
1
2
3
4
5
6
7
8
CC
(300-mil)
DS1005
15
14
16
13
12
11
10
9
111799
NC
V
NC
NC
NC
TAP 1
TAP 3
TAP 5
CC

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DS1005M-100 Summary of contents

Page 1

... GND TAP 5 DS1005 14-Pin DIP (300-mil) GND See Mech. Drawings Section See Mech. Drawings Section TAP 2 TAP 4 3 GND 4 DS1005M 8-Pin DIP (300-mil) See Mech. Drawings Section PIN DESCRIPTION TAP 1-TAP 5 - TAP Output Number Volts CC GND - Ground Connection IN - Input DS1005 IN ...

Page 2

LOGIC DIAGRAM Figure 1 PART NUMBER DELAY TABLE (t PART NO. TAP 1 DS1005- DS1005- DS1005-100 20 ns DS1005-125 25 ns DS1005-150 30 ns DS1005-175 35 ns DS1005-200 40 ns DS1005-250 50 ns Custom delays available ...

Page 3

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current * This is a stress rating only and functional operation of the device at these or any other conditions above ...

Page 4

NOTES: 1. All voltages are referenced to ground. 2. Measured with outputs open Delays accurate on both rising and falling edges within 3%, whichever CC is greater. 4. See Test ...

Page 5

TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1005. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter ...

Page 6

TIMING DIAGRAM: SILICON DELAY LINE Figure 2 DALLAS SEMICONDUCTOR TEST CIRCUIT Figure DS1005 ...

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