M4T32-BR12SH1 STMicroelectronics, M4T32-BR12SH1 Datasheet - Page 10

IC SNAPHAT BATT/CRYSTAL 28-SOIC

M4T32-BR12SH1

Manufacturer Part Number
M4T32-BR12SH1
Description
IC SNAPHAT BATT/CRYSTAL 28-SOIC
Manufacturer
STMicroelectronics

Specifications of M4T32-BR12SH1

Battery Type
Li-(CF)
Operating Supply Voltage
0 V to 2.8 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
SOIC-28
Mounting Style
SMD/SMT
Capacity
120 mAh
Chemical System
Lithium Poly-Carbonmonoflouride
Primary Type
Pack
Size
Cylindrical
Standards
UL Recognized
Temperature, Operating
0 to +75 °C
Temperature, Operating, Maximum
70 °C
Temperature, Operating, Minimum
0 °C
Termination
Snap-On
Voltage, Battery
3 V
Voltage, Rating
3 V
Supply Voltage Range
2.8V
Battery Ic Case Style
SOIC
No. Of Pins
4
Operating Temperature Range
0°C To +70°C
Crystal Terminals
Snap On
Load Capacitance
12.5pF
Rohs Compliant
Yes
Crystal Mounting Type
SMD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-3687-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M4T32-BR12SH1
Manufacturer:
ST
Quantity:
115
Part Number:
M4T32-BR12SH1
Manufacturer:
GRENERGY
Quantity:
2 000
Part Number:
M4T32-BR12SH1
Manufacturer:
ST
Quantity:
20 000
Operation modes
2.2
10/29
WRITE mode
The M48T35AV is in the WRITE mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t
cycles to avoid bus contention; however, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
Figure 6.
Figure 7.
A0-A14
E
W
DQ0-DQ7
A0-A14
E
W
DQ0-DQ7
WRITE enable controlled, WRITE mode AC waveform
Chip enable controlled, WRITE mode AC waveforms
tAVEL
tAVEL
tAVWL
tAVWL
Doc ID 6845 Rev 8
tWLQZ
EHAX
WHDX
tAVWH
from chip enable or t
tAVEH
afterward. G should be kept high during WRITE
tWLWH
VALID
tAVAV
WLQZ
tAVAV
VALID
tELEH
after W falls.
tDVEH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
WHAX
from WRITE enable prior
tEHDX
tWHQX
DVWH
tEHAX
tWHAX
prior to the
M48T35AV
AI00926
AI00927

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