IC SNAPHAT BATT/CRYSTAL 28-SOIC

M4T32-BR12SH1

Manufacturer Part NumberM4T32-BR12SH1
DescriptionIC SNAPHAT BATT/CRYSTAL 28-SOIC
ManufacturerSTMicroelectronics
M4T32-BR12SH1 datasheets
MSDS Material Safety Datasheet
 

Specifications of M4T32-BR12SH1

Battery TypeLi-(CF)Operating Supply Voltage0 V to 2.8 V
Maximum Operating Temperature+ 70 CMinimum Operating Temperature0 C
Package / CaseSOIC-28Mounting StyleSMD/SMT
Capacity120 mAhChemical SystemLithium Poly-Carbonmonoflouride
Primary TypePackSizeCylindrical
StandardsUL RecognizedTemperature, Operating0 to +75 °C
Temperature, Operating, Maximum70 °CTemperature, Operating, Minimum0 °C
TerminationSnap-OnVoltage, Battery3 V
Voltage, Rating3 VSupply Voltage Range2.8V
Battery Ic Case StyleSOICNo. Of Pins4
Operating Temperature Range0°C To +70°CCrystal TerminalsSnap On
Load Capacitance12.5pFRohs CompliantYes
Crystal Mounting TypeSMDLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names497-3687-5  
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Operation modes
2.2
WRITE mode
The M48T35AV is in the WRITE mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t
cycles to avoid bus contention; however, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
Figure 6.
WRITE enable controlled, WRITE mode AC waveform
A0-A14
E
W
DQ0-DQ7
Figure 7.
Chip enable controlled, WRITE mode AC waveforms
A0-A14
E
W
DQ0-DQ7
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from chip enable or t
EHAX
afterward. G should be kept high during WRITE
WHDX
after W falls.
WLQZ
tAVAV
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tAVAV
VALID
tAVEH
tAVEL
tELEH
tAVWL
tDVEH
Doc ID 6845 Rev 8
M48T35AV
from WRITE enable prior
WHAX
prior to the
DVWH
tWHAX
tWHQX
tWHDX
DATA INPUT
tDVWH
tEHAX
tEHDX
DATA INPUT
AI00926
AI00927