IC SNAPHAT BATT/CRYSTAL 28-SOIC

M4T32-BR12SH1

Manufacturer Part NumberM4T32-BR12SH1
DescriptionIC SNAPHAT BATT/CRYSTAL 28-SOIC
ManufacturerSTMicroelectronics
M4T32-BR12SH1 datasheets
MSDS Material Safety Datasheet
 

Specifications of M4T32-BR12SH1

Battery TypeLi-(CF)Operating Supply Voltage0 V to 2.8 V
Maximum Operating Temperature+ 70 CMinimum Operating Temperature0 C
Package / CaseSOIC-28Mounting StyleSMD/SMT
Capacity120 mAhChemical SystemLithium Poly-Carbonmonoflouride
Primary TypePackSizeCylindrical
StandardsUL RecognizedTemperature, Operating0 to +75 °C
Temperature, Operating, Maximum70 °CTemperature, Operating, Minimum0 °C
TerminationSnap-OnVoltage, Battery3 V
Voltage, Rating3 VSupply Voltage Range2.8V
Battery Ic Case StyleSOICNo. Of Pins4
Operating Temperature Range0°C To +70°CCrystal TerminalsSnap On
Load Capacitance12.5pFRohs CompliantYes
Crystal Mounting TypeSMDLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names497-3687-5  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Page 8/29

Download datasheet (513Kb)Embed
PrevNext
Operation modes
2
Operation modes
As
Figure 4 on page 7
oscillator of the M48T35AV are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 7FF8h-7FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 7FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T35AV includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T35AV also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 3 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
battery backup switchover voltage (V
maintains data and clock operation until valid power returns.
Table 2.
Operating modes
Mode
Deselect
WRITE
READ
READ
Deselect
V
SO
Deselect
1. See
Table 11 on page 21
Note:
X = V
or V
; V
IH
IL
SO
2.1
READ mode
The M48T35AV is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 15 address inputs defines which one of
the 32,768 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within address access time (t
the E and G access times are also satisfied.
If the E and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
8/29
shows, the static memory array and the quartz controlled clock
), the control circuitry connects the battery which
SO
V
E
G
CC
V
X
IH
V
X
IL
3.0 to 3.6 V
V
V
IL
IL
V
V
IL
IH
(1)
to V
(min)
X
X
PFD
≤ V
(1)
X
X
SO
for details.
= Battery backup switchover voltage.
) after the last address input signal is stable, providing that
AVQV
) or output enable access time (t
ELQV
Doc ID 6845 Rev 8
M48T35AV
is out of
CC
. As V
falls below the
CC
CC
W
DQ0-DQ7
Power
X
High Z
Standby
V
D
Active
IL
IN
V
D
Active
IH
OUT
V
High Z
Active
IH
X
High Z
CMOS standby
Battery backup
X
High Z
mode
).
GLQV