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... Z80 Family CPU User Manual User Manual UM008005-0205 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com ...
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... Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded ...
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Revision History Each instance in Table 1 reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table. Table 1. Revision History of this Document Revision Date Level Section December ...
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Z80 CPU User’s Manual iv UM008005-0205 PRELIMINARY DRAFT v1.0 Chapter Title ...
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Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Z80 CPU User’s Manual vi Adding RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Instructions ADC ...
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Z80 CPU User’s Manual ...
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LD (BC ...
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Z80 CPU User’s Manual xii LD SP ...
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RRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Z80 CPU User’s Manual xiv List of Instructions UM008005-0205 ...
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List of Figures Figure 1. Z80 CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Figure 2. ...
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Z80 CPU User’s Manual xvi List of Figures UM008005-0205 ...
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List of Tables Table 1. Revision History of this Document . . . . . . . . . . . . . . . . . . . . . iii Table 2. Interrupt Enable/Disable, Flip-Flops . . . ...
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Z80 CPU User’s Manual xviii List of Tables UM008005-0205 ...
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... Intended Audience This document is written for ZiLOG customers who are experienced at working with microprocessors or in writing assembly code or compilers. Manual Organization The Z80 CPU User’s Manual is divided into four chapters. ...
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User’s Manual Z80 CPU xx Z80 CPU Instruction Description Presents the User’s Manual instruction types, addressing modes and instruction Op Codes. Z80 Instruction Set Presents an overview of the User’s Manual assenbly language, status indicator flags and the Z80 instructions. ...
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Use of the Terms LSB and MSB In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms, msb and lsb, mean least significant bit and ...
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... User’s Manual Z80 CPU xxii Register Access Abbreviations Register access is designated by the following abbreviations: Designation R R/W W – Trademarks Z80, Z180, Z380 and Z80382 are trademarks of ZiLOG, Inc. UM008005-0205 Description Read Only Read/Write Write Only Unspecified or indeterminate Manual Objectives ...
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... Overview ARCHITECTURE The ZiLOG Z80 CPU family of components are fourth-generation enhanced microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and third-generation microprocessors. The speed offerings from 6– 20 MHz suit a wide range of applications which migrate software. The internal registers contain 208 bits of read/write memory that are accessible to the programmer ...
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Z80 CPU User’s Manual 2 13 CPU and System Control Signals Figure 1. CPU Registers The Z80 CPU contains 208 bits of R/W memory that are available to the programmer. Figure 2 illustrates how this memory is configured to eighteen ...
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Main Register Set Accumulator Interrupt Vector I Index Register Index Register Stack Pointer Program Counter Figure 2. Special-Purpose Registers Program Counter (PC) The program counter holds the 16-bit address of the current instruction being fetched from ...
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Z80 CPU User’s Manual 4 unlimited subroutine nesting and simplification of many types of data manipulation. Two Index Registers (IX and IY) The two independent index registers hold a 16-bit base address that is used in indexed addressing modes. In ...
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Accumulator and Flag Registers The CPU includes two independent 8-bit accumulators and associated 8-bit flag registers. The accumulator holds the results of 8-bit arithmetic or logical operations while the 1 16-bit operations, such as indicating whether or not the result ...
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Z80 CPU User’s Manual 6 • Add • Subtract • Logical AND • Logical OR • Logical Exclusive OR • Compare • Left or Right Shifts or Rotates (Arithmetic and Logical) • Increment • Decrement • Set Bit • Reset ...
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M1 MREQ IORQ System Control RD WR RFSH HALT WAIT CPU Control INT NMI RESET CPU BUSRQ Bus BUSACK Control CLK +5V GND Figure 3. Pin Functions A15–A0 Address Bus (output, active High, tristate). A15-A0 form a 16-bit address bus. ...
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Z80 CPU User’s Manual 8 BUSACK Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ RD, and WR have entered their high-impedance states. The external ...
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IORQ Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge ...
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Z80 CPU User’s Manual 10 interrupt status to Mode 0. During reset time, the address and data bus high-impedance state, and all control output signals go to the inactive state. Notice that RESET must be active for ...
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TIMING Overview The Z80 CPU executes instructions by stepping through a precise set of basic operations. These include: • Memory Read or Write • I/O Device Read or Write • Interrupt Acknowledge All instructions are series of basic operations. Each ...
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Z80 CPU User’s Manual 12 T Cycle CLK T1 T2 Machine Cycle (Opcode Fetch) Figure 4. Instruction Fetch Figure 5 depicts the timing during an M1 (opcode fetch) cycle. The PC is placed on the address bus at the beginning ...
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The MREQ signal during refresh time should be used to perform a refresh read of all memory elements. The refresh signal can not be used by itself because the refresh address is ...
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Z80 CPU User’s Manual 14 it can be used directly as a R/W pulse to virtually any type of semiconductor memory. Furthermore, the WR signal goes inactive one-half T state before the address and data bus contents are changed so ...
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CLK A — IORQ RD D — WAIT WR D — *Automatically inserted WAIT state Figure 7. Bus Request/Acknowledge Cycle Figure 8 illustrates the timing for a Bus Request/Acknowledge cycle. The ...
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Z80 CPU User’s Manual 16 are transferred under DMA control. During a bus request cycle, the CPU cannot be interrupted by either an NMI or an INT signal. CLK BUSREQ BUSACK A — — ...
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Last M Cycle of Instruction CLK INT A — MREQ IORQ D — WAIT RD Figure 9. Non-Maskable Interrupt Response Figure 10 illustrates the request/acknowledge cycle for the non-maskable interrupt. This signal is ...
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Z80 CPU User’s Manual 18 CLK NMI A — MREQ RD RFSH Figure 10. Non-Maskable Interrupt Request Operation HALT Exit Whenever a software HALT instruction is executed, the CPU executes NOPs until an interrupt is received ...
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CLK HALT RD or NMI HALT Instruction is repeated during this Memory Cycle Figure 11. HALT Exit Power-Down Acknowledge Cycle When the clock input to the CMOS Z80 CPU is stopped at either a High or Low ...
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Z80 CPU User’s Manual 20 Power-Down Release Cycle The system clock must be supplied to the CMOS Z80 CPU to release the power-down state. When the system clock is supplied to the CLK input, the CMOS Z80 CPU restarts operations ...
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CLK INT M1 HALT Figure 15. Power-Down Release Cycle No. 3 UM008005-0205 Z80 CPU User’s Manual Overview ...
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Z80 CPU User’s Manual 22 INTERRUPT RESPONSE Overview An interrupt allows peripheral devices to suspend CPU operation and force the CPU to start a peripheral service routine. This service routine usually involves the exchange of data, status, or control information ...
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A CPU reset forces both the IFF1 and IFF2 to the reset state, which disables interrupts. Interrupts can be enabled at any time instruction from the programmer. When an EI instruction is executed, any pending interrupt request ...
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Z80 CPU User’s Manual 24 Table 2. Interrupt Enable/Disable, Flip-Flops Action DI Instruction Execution EI Instruction Execution LD A,I Instruction Execution * LD A,R instruction Execution * Accept NMI RETN Instruction Execution IFF2 * CPU Response Non-Maskable The CPU always ...
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The number of clock cycles necessary to execute this instruction is two more than the normal number for the instruction. This occurs because the CPU automatically ...
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Z80 CPU User’s Manual 26 because the pointer is used to get two adjacent bytes to form a complete 16- bit service routine starting address and the addresses must always start in even locations. Interrupt Service Routine Starting Address Table ...
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Hardware and Software Implementation Examples HARDWARE Minimum System This chapter is an introduction to implementing systems that use the Z80 CPU. Figure 17 illustrates a simple Z80 system. Any Z80 system must include the following elements: • 5V Power Supply ...
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Z80 CPU User’s Manual 28 +5V RESET Figure 17. Minimum Z80 Computer System Because the Z80 CPU requires only a single 5V power supply, most small systems can be implemented using only this single supply. The external memory can be ...
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Adding RAM Most computer systems require some external Read/Write memory for data storage and stack implementation. Figure 18 illustrates how 256 bytes of static memory are added to the previous example in Figure 17. The memory space is assumed to ...
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Z80 CPU User’s Manual 30 Memory Speed Control Slow memories can reduce costs for many applications. The WAIT line on the CPU allows the Z80 to operate with any speed memory. Memory access time requirements, which are covered in Chapter ...
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... Figure 20. Adding One Wait State to Any Memory Cycle Interfacing Dynamic Memories Each individual dynamic RAM has it’s own specifications that require minor modifications to the examples given here. ZiLOG Application Notes are available describing how the Z80 CPU is interfaced with most popular dynamic RAM. ...
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Z80 CPU User’s Manual 32 RFSH MREQ – – Figure 21. Interfacing Dynamic RAMs UM008005-0205 RAM Array R/W Data Bus RAM Array R/W (0000 to ...
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SOFTWARE IMPLEMENTATION EXAMPLES Overview of Software Features The Z80 instruction set provides the user with a large number of operations to control the Z80 CPU. The main alternate and index registers can hold arithmetic and logical operations, form memory addresses, ...
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Z80 CPU User’s Manual 34 After the execution of an instruction that sets a flag, that flag can be used to control a conditional jump or return instruction. These instructions provide logical control following the manipulation of single bit, 8-bit ...
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Example Two: A string in memory (limited to a maximum length of 132 characters) starting at location DATA moved to another memory location starting at location BUFFER until an ASCII $ (used as a string delimitor) is ...
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Z80 CPU User’s Manual 36 Eleven bytes are required for this operation. Figure 22. Shifting of BCD Digits/Bytes Example Four: One number subtracted from another number, both of which are in packed BCD format and are of ...
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DAA VALUE LD INC INC DJNZ SUBDEC - $;DECREMENT B AND GO TO "SUBDEC" Seventeen bytes are required for this operation. Examples of Programming Tasks As depicted in Table 3, this example program sorts an array of numbers to ascending ...
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Z80 CPU User’s Manual 38 Table 3. Bubble Listing (Continued) Loc Obj Code Stmt Source Statement 0000 222600 23 0003 cb84 24 0005 41 25 0006 05 26 0007 dd2a2600 27 000b ...
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Table 3. Bubble Listing (Continued) Loc Obj Code Stmt Source Statement 0026 43 flag: equ 0026 44 data: defs 45 The following program (see Table 4) multiplies two unsigned 16-bit integers, leaving the result in the HL register pair. Table ...
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Z80 CPU User’s Manual 40 Table 4. Multiply Listing (Continued) Obj Loc Code 0000 0610 0002 4a 0003 7b 0004 eb 0005 210000 0008 cb39 000a if 000b 3001 good 19 000e eb goof 29 0010 eb 0011 10f5 0013 ...
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Z80 CPU Instruction Description Overview The Z80 CPU can execute 158 different instruction types including all 78 of the 8080A CPU. The instructions fall into these major groups: • Load and Exchange • Block Transfer and Search • Arithmetic and ...
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Z80 CPU User’s Manual 42 A unique set of block transfer instructions is provided in the Z80. With a single instruction, a block of memory of any size can be moved to any other location in memory. This set of ...
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Op Code. This is possible because only eight separate addresses located in page zero of the external memory may be specified. Program jumps may also be achieved by loading register HL, IX directly into the PC, ...
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Z80 CPU User’s Manual 44 Addressing Modes Most of the Z80 instructions operate on data stored in internal CPU registers, external memory the I/O ports. Addressing refers to how the address of this data is generated in each ...
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Modified Page Zero Addressing The Z80 has a special single byte locations in page zero of memory. This instruction, which is referred restart, sets the effective address in page zero. The value of this ...
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Z80 CPU User’s Manual 46 Extended Addressing Extended Addressing provides for two bytes (16 bits) of address to be included in the instruction. This data can be an address to which a program can jump or it can be an ...
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The displacement is a signed two’s complement number. Indexed addressing greatly simplifies programs using tables of data because the index register can point to the start of any table. Two index registers are provided because very often operations require two ...
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Z80 CPU User’s Manual 48 except that a displacement is added with indexed addressing. Register indirect addressing allows for very powerful but simple to implement memory accesses. The block move and search commands in the Z80 are extensions of this ...
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Also depicted is the assembly language mnemonic that is used for each instruction. All instruction Op Codes are listed in hexadecimal notation. Single byte Op Codes require two hex characters while double byte Op Codes require four hex characters. For ...
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Z80 CPU User’s Manual 50 Table 6 defines the Op Code for all the 8-bit load instructions implemented in the Z80 CPU. Also described in this table is the type of addressing used for each instruction. The source of the ...
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Table 6. 8-Bit Load Group LD Source Implied Register Destination Register ...
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Z80 CPU User’s Manual 52 All load instructions using indexed addressing for either the source or destination location actually use three bytes of memory with the third byte being the displacement d. For example, a load register E with the ...
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Loading a memory location using indexed addressing for the destination and immediate addressing for the source requires four bytes. For example, LD (IX - 15), 21H appears as: Address A+1 A+2 F1 A+3 21 Notice that with ...
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Z80 CPU User’s Manual 54 (SP) (SP+1) • • The POP instructions utilize a 16-bit operand and the high order byte is always pushed first and popped last. PUSH BC PUSH DE PUSH HL POP HL The instruction using extended ...
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Table 7. 16-Bit Load Group LD, PUSH and POP Register EXT (nn) ED ADDR PUSH REG. (SP Instructions → IND. NOTE: The Push & Pop instruction ...
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Z80 CPU User’s Manual 56 Table 8. Exchanges EX and EXX IMPLIED REG. IND. Block Transfer and Search Table 9 lists the extremely powerful block transfer instructions. These instructions operate with three registers. • HL • DE • BC After ...
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Because 16-bit registers are used, the size of the block can Kbytes (1K = 1024) long and can be moved from any location in memory to any other location. Furthermore, the blocks can be overlapping because ...
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Z80 CPU User’s Manual 58 Table 9. Block Transfer Group Destination Reg. Indir. Table 10. Block Search Group Search Location Reg. Indir. (HL) (ED) A1 (ED) B1 (ED) A9 (ED) B9 Note: HL points to location in memory to be ...
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In all these instructions, except DEC specified 8-bit operation is performed between the data in the accumulator and the source data. The result of the operation is placed in the accumulator with the exception of compare ( ...
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Z80 CPU User’s Manual 60 Five general-purpose arithmetic instructions operate on the accumulator or carry flag. These five are listed in Table 12. The decimal adjust instruction can adjust for subtraction as well as addition, making BCD arithmetic operations simple. ...
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Table 11. 8-Bit Arithmetic and Logic (Continued) OR COMPARE CP INCREMENT INC DECREMENT DEC Table 12. General-Purpose AF Operation Decimal Adjust Acc, DAA Complement Acc, CPL Negate Acc, NEG (2’s complement Complement Carry Flag, CCF Set Carry Flag, SCF Table ...
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Z80 CPU User’s Manual 62 Table 13. 16-Bit Arithmetic (Continued) Destination Rotate and Shift A major feature of the Z80 is to rotate or shift data in the accumulator, any general-purpose register, or any memory location. All the rotate and ...
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Table 14. Rotates and Shifts Source Type (HL) (IX+d) (lY+d) of Rotate Shift RCL RRC CB CB ...
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Z80 CPU User’s Manual 64 conditions, or data packed into memory locations, making memory utilization more efficient. The Z80 can set, reset, or test any bit in the accumulator, any general- purpose register or any memory location with a single ...
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Three types of register indirect jumps are also included. These instructions are implemented by loading the register pair HL or one of the index registers directly into the PC. This feature allows for program jumps to be ...
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Z80 CPU User’s Manual 66 Table 15. Bit Manipulation Group (Continued) Test 0 Bit UM008005-0205 Register Addressing ...
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Table 15. Bit Manipulation Group (Continued) Register Addressing Rest Bit 0 C8 RES UM008005-0205 ...
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Z80 CPU User’s Manual 68 Table 15. Bit Manipulation Group (Continued) Set Bit 0 SET UM008005-0205 Register Addressing ...
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Table 16. Jump, Call, and Return Group JUMP JP IMMED. EXT. JUMP JR RELATIVE JUMP JP Register INDIR. CALL IMMED. EXT. Decrement B, Jump RELATIVE If Non Zero DJNZ Return RE REGISTER INDIR. Return From INT RETI Return From Non ...
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Z80 CPU User’s Manual 70 Table 17 lists the eight Op Codes for the restart instruction. This instruction is a single byte call to any of the eight addresses listed. The simple mnemonic for these eight calls is also listed. ...
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In all register indirect input output instructions, including block I/O transfers, the content of register C is transferred to the lower half of the address bus (device address) while the ...
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Z80 CPU User’s Manual 72 Table 18. Input Group Input Input IN Destination INI - input & inc HL, Dec B INIR - INP, Inc HL, Dec B, repeat IF B≠0 IND - input & Inc Dec HL, Dec B ...
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Table 19. 8-Bit Arithmetic and Logic 11OUT Immed. Reg Ind. 11OUT - output inc HL, dec B 11OUT - output dec B, repeat if B≠0 11OUT - output dec HL and B 11OUTDR - output, dec HL and B, repeat ...
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Z80 CPU User’s Manual 74 UM008005-0205 Z80 CPU Instruction Description ...
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... Z80 CPU. ZiLOG provides several assemblers that differ in the features offered. Both absolute and relocatable assemblers are available with the Development and Micro-computer Systems. The absolute assembler is ...
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Z80 CPU User’s Manual 76 Z80 Status Indicator Flags The flag registers (F and F') supply information to the user about the status of the Z80 at any given time. The bit positions for each flag is listed below: 7 ...
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Also, the Flag if the conditions for making the decimal adjustment are met. For instructions between the least significant byte (LSB) and most significant byte (MSB) for any register or memory location. During instructions , the ...
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Z80 CPU User’s Manual less than the minimum possible number (– +127 condition is determined by examining the sign bits of the operands. For addition, operands with different signs never cause Overflow. When adding operands ...
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Byte Count Register ( decrements to During the interrupt enable flip-flop ( When inputting a byte from an I/O device with an the P/V Flag is adjusted to indicate the data parity. Half Carry Flag The ...
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Z80 CPU User’s Manual 80 When inputting or outputting a byte between a memory location and an I/O device ( Register is from I/O devices using Sign Flag The Sign Flag (S) stores the state of the most-significant bit of ...
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Load Group r, ← r' Operation: Op Code: LD Operands Description: The contents of any register r' are loaded to any other register identifies any of the registers ...
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Z80 CPU User’s Manual 82 r ← n Operation: Op Code: LD Operands Description: The 8-bit integer n is loaded to any register r, where r identifies register assembled ...
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Operation: Op Code: LD Operands: r, (HL Description: The 8-bit contents of memory location (HL) are loaded to register r, where r identifies register assembled as follows ...
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Z80 CPU User’s Manual 84 r ← (IX+d) Operation: Op Code: LD Operands: r, (IX+ Description: The operand (IX+d), (the contents of the Index Register IX summed with a two’s complement displacement integer d) is loaded ...
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Operation: Op Code: LD Operands: r, (lY+ Description: The operand (lY+d) (the contents of the Index Register IY summed with a two’s complement displacement integer (d) is loaded to register r, where r ...
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Z80 CPU User’s Manual 86 (HL) ← r Operation: Op Code: LD Operands: (HL Description: The contents of register r are loaded to the memory location specified by the contents of the HL register pair. The symbol ...
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Operation: Op Code: LD Operands: (IX+d Description: The contents of register r are loaded to the memory address specified by the contents of Index Register IX summed with d, a two’s complement ...
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Z80 CPU User’s Manual 88 (lY+d) ← r Operation: Op Code: LD Operands: (lY+d Description: The contents of resister r are loaded to the memory address specified by the sum of the contents of the Index ...
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Operation: Op Code: LD Operands: (HL Description: Integer is loaded to the memory address specified by the contents of the n HL register pair. M Cycles Condition Bits Affected: None Example: If the HL ...
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Z80 CPU User’s Manual 90 (IX+d) ← n Operation: Op Code: LD Operands: (IX+d Description: The operand is loaded to the memory address specified by the sum of the n Index Register IX and the ...
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Operation: Op Code: LD Operands: (lY+d Description: Integer n is loaded to the memory location specified by the contents of the Index Register summed with the two’s complement displacement integer d. M ...
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Z80 CPU User’s Manual 92 A ← (BC) Operation: Op Code: LD Operands: A, (BC Description: The contents of the memory location specified by the contents of the BC register pair are loaded to the Accumulator. Condition Bits ...
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A ← (DE) Operation: Op Code: LD Operands: A, (DE Description: The contents of the memory location specified by the register pair DE are loaded to the Accumulator. M Cycles Condition Bits Affected: None Example: If the DE ...
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Z80 CPU User’s Manual 94 A ← (nn) Operation: Op Code: LD Operands: A, (nn Description: The contents of the memory location specified by the operands loaded to the Accumulator. The first order byte of a 2-byte memory ...
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A Operation: Op Code: LD Operands: (BC Description: The contents of the Accumulator are loaded to the memory location specified by the contents of the register pair BC. M Cycles Condition Bits Affected: None Example: ...
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Z80 CPU User’s Manual 96 (DE) ← A Operation: Op Code: LD Operands: (DE Description: The contents of the Accumulator are loaded to the memory location specified by the contents of the DE register pair. Condition Bits Affected: ...
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A Operation: Op Code: LD Operands: (nn Description: The contents of the Accumulator are loaded to the memory address specified by the operand low order byte of M Cycles Condition Bits Affected: None Example: If ...
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Z80 CPU User’s Manual 98 A ← 1 Operation: Op Code: LD Operands Description: The contents of the Interrupt Vector Register I are loaded to the Accumulator. Condition Bits Affected interrupt occurs ...
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A, ← R Operation: Op Code: LD Operands Description: The contents of Memory Refresh Register R are loaded to the Accumulator. M Cycles Condition Bits Affected set if, R-Register is negative; reset ...
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Z80 CPU User’s Manual 100 I ← A Operation: Op Code: LD Operands Description: The contents of the Accumulator are loaded to the Interrupt Control Vector Register, I. Condition Bits Affected: None UM008005-0205 LD I,A 1 ...
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R ← A Operation: Op Code: LD Operands Description: The contents of the Accumulator are loaded to the Memory Refresh register R. M Cycles Condition Bits Affected: None UM008005-0205 ...
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Z80 CPU User’s Manual 102 16-Bit Load Group dd ← nn Operation: Op Code: LD Operands: dd Description: The 2-byte integer BC, DE, HL register pairs, assembled as follows in the object code: The first Condition ...
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Ix ← nn Operation: Op Code: LD Operands: IX Description: Integer nn Op Code is the low order byte. M Cycles Condition Bits Affected: None Example: At instruction UM008005-0205 LD IX ...
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Z80 CPU User’s Manual 104 IY ← nn Operation: Op Code: LD Operands: IY Description: Integer Op Code is the low order byte. Condition Bits Affected: None Example: At instruction 7733H UM008005-0205 LD IY ...
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H ← (nn+1), L ← (nn) Operation: Op Code: LD Operands: HL, (nn Description: The contents of memory address ( register pair HL (register L), and the contents of the next highest memory address ( nn first operand ...
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Z80 CPU User’s Manual 106 ddh ← (nn+1) ddl ← (nn) Operation: Op Code: LD Operands: dd, (nn Description: The contents of address ( pair dd, and the contents of the next highest memory address ( loaded to ...
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IXh ← (nn+1), IXI ← (nn) Operation: Op Code: LD Operands: IX, (nn Description: The contents of the address ( Index Register IX, and the contents of the next highest memory address ( +1) are loaded ...
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Z80 CPU User’s Manual 108 IYh ← (nn+1), IYI ← nn) Operation: Op Code: LD Operands: IY, (nn Description: The contents of address ( Register IY, and the contents of the next highest memory address ( are loaded ...
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H, (nn) ← L Operation: Op Code: LD Operands: (nn Description: The contents of the low order portion of register pair HL (register L) are loaded to memory address ( of HL (register H) are ...
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Z80 CPU User’s Manual 110 (nn+1) ← ddh, (nn) ← ddl Operation: Op Code: LD Operands: (nn Description: The low order byte of register pair dd is loaded to memory address ( upper byte is loaded to ...
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IXh, (nn) ← IXI Operation: Op Code: LD Operands: (nn Description: The low order byte in Index Register IX is loaded to memory address ( the upper order byte is loaded to the ...
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Z80 CPU User’s Manual 112 (nn+1) ← IYh, (nn) ← IYI Operation: Op Code: LD Operands: (nn Description: The low order byte in Index Register IY is loaded to memory address ( the upper order byte is ...
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SP ← HL Operation: Op Code: LD Operands: SP Description: The contents of the register pair HL are loaded to the Stack Pointer (SP). M Cycles Condition Bits Affected: None Example: If the register pair HL contains ...
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Z80 CPU User’s Manual 114 SP ← Operation: Op Code: LD Operands: SP Description: The 2-byte contents of Index Register IX are loaded to the Stack Pointer (SP). Condition Bits Affected: None Example: If the ...
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SP ← IY Operation: Op Code: LD Operands: SP Description: The 2-byte contents of Index Register IY are loaded to the Stack Pointer SP. M Cycles Condition Bits Affected: None Example: If Index Register IY ...
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Z80 CPU User’s Manual 116 (SP-2) ← qqL, (SP-1) ← qqH Operation: Op Code: PUSH Operands Description: The contents of the register pair qq are pushed to the external memory LIFO (last-in, first-out) Stack. The Stack Pointer (SP) ...
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IXL, (SP-1) ← IXH Operation: Op Code: PUSH Operands Description: The contents of the Index Register IX are pushed to the external memory LIFO (last-in, first-out) Stack. The Stack Pointer (SP) register pair ...
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Z80 CPU User’s Manual 118 (SP-2) ← IYL, (SP-1) ← IYH Operation: Op Code: PUSH Operands Description: The contents of the Index Register IY are pushed to the external memory LIFO (last-in, first-out) Stack. The Stack Pointer ...
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Operation: Op Code: POP Operands Description: The top two bytes of the external memory LIFO (last-in, first-out) Stack are popped to register pair qq. The Stack Pointer (SP) register pair holds ...
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Z80 CPU User’s Manual 120 IXH ← (SP+1), IXL ← (SP) Operation: Op Code: POP Operands Description: The top two bytes of the external memory LIFO (last-in, first-out) Stack are popped to Index Register IX. The Stack ...
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IYH ← (SP-X1), IYL ← (SP) Operation: Op Code: POP Operands Description: The top two bytes of the external memory LIFO (last-in, first-out) Stack are popped to Index Register IY. The Stack Pointer (SP) register ...
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Z80 CPU User’s Manual 122 Exchange, Block Transfer, and Search Group DE ↔ HL Operation: Op Code: EX Operands: DE Description: The 2-byte contents of register pairs DE and HL are exchanged. Condition Bits Affected: None Example: If ...
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AF ↔ AF' Operation: Op Code: EX Operands: AF, AF Description: The 2-byte contents of the register pairs AF and AF are exchanged. Register pair AF consists of registers A' and F'. M Cycles Condition Bits Affected: None ...
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Z80 CPU User’s Manual 124 (BC) ↔ (BC'), (DE) ↔ (DE'), (HL) ↔ (HL') Operation: Op Code: EXX Operands: — 1 Description: Each 2-byte value in register pairs BC, DE, and HL is exchanged with the 2-byte value in BC', ...
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H ↔ (SP+1), L ↔ (SP) Operation: Op Code: EX Operands: (SP Description: The low order byte contained in register pair HL is exchanged with the contents of the memory address specified by the contents of register ...
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Z80 CPU User’s Manual 126 IXH ↔ (SP+1), IXL ↔ (SP) Operation: Op Code: EX Operands: (SP Description: The low order byte in Index Register IX is exchanged with the contents of the memory address specified by ...
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IYH ↔ (SP+1), IYL ↔ (SP) Operation: Op Code: EX Operands: (SP Description: The low order byte in Index Register IY is exchanged with the contents of the memory address specified by the contents of ...
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Z80 CPU User’s Manual 128 (DE) ← (HL), DE ← ← ← Operation: Op Code: LDI Operands: (SP Description: A byte of data is transferred from the ...
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DE ← ← F↔ Operation: Op Code: LDIR Operands Description: This 2-byte instruction transfers a byte of data from the memory location ...
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Z80 CPU User’s Manual 130 Example: If the HL register pair contains 2222H these contents: (1111H) contains (1112H) contains (1113H) contains then at execution of locations are (1111H) contains (1112H) contains (1113H) contains UM008005-0205 11111H , the ...
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DE ← DE -1, HL ← HL-1, BC ← BC-1 Operation: Op Code: LDD Operands: — Description: This 2-byte instruction transfers a byte of data from the memory location addressed by the contents ...
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Z80 CPU User’s Manual 132 (DE) ← (HL), DE ← D ← ← HL-1, BC ← BC-1 Operation: Op Code: LDDR Operands: — Description: This 2-byte instruction transfers a byte of data from the memory location ...
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Example: If the HL register pair contains , the BC register pair contains 2225H these contents: ( 1114H ( 1113H ( 1112H Then at execution of locations are 1114H ( 1113H ( 1112H UM008005-0205 , the ...
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Z80 CPU User’s Manual 134 A- (HL), HL ← HL +1, BC ← Operation: Op Code: CPI Operands: — Description: The contents of the memory location addressed by the HL register is compared with the contents ...
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A-(HL), HL ← HL+1, BC ← BC-1 Operation: Op Code: CPIR Operands: — Description: The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator. In case ...
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Z80 CPU User’s Manual 136 Example: If the HL register pair contains Byte Counter contains Then, at execution of contents of the Byte Counter is and the Z flag in the F register sets. UM008005-0205 1111H , and memory locations ...
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A -(HL), HL ← HL -1, BC ← Operation: Op Code: CPD Operands: — Description: The contents of the memory location addressed by the HL register pair is compared with the contents of the ...
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Z80 CPU User’s Manual 138 A -(HL), HL ← HL -1, BC ← Operation: Op Code: CPDR Operands: — Description: The contents of the memory location addressed by the HL register pair is compared with the ...
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Example: If the HL register pair contains Byte Counter contains ( 1118H ( 1117H ( 1116H Then, at execution of the contents of the Byte Counter are sets, and the Z flag in the F register sets. UM008005-0205 , the ...
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Z80 CPU User’s Manual 140 8-Bit Arithmetic Group A ← Operation: Op Code: ADD Operands Description: The contents of register r are added to the contents of the Accumulator, and the result is stored ...
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Example: If the contents of the Accumulator are are , at execution of 11H . 55H UM008005-0205 , and the contents of register C 44H the contents of the Accumulator are ADD A,C Z80 CPU User’s Manual 141 Z80 Instruction ...
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Z80 CPU User’s Manual 142 A ← Operation: Op Code: ADD Operands Description: The integer n is added to the contents of the Accumulator, and the results are stored in the Accumulator. Condition Bits ...
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A ← (HL) Operation: Op Code: ADD Operands: A, (HL Description: The byte at the memory address specified by the contents of the HL register pair is added to the contents of the Accumulator, and the ...
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Z80 CPU User’s Manual 144 A ← (IX+d) Operation: Op Code: ADD Operands Description: The contents of the Index Register (register pair IX) is added to a two’s complement displacement d to ...
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A ← (ID+d) Operation: Op Code: ADD Operands Description: The contents of the Index Register (register pair IY) is added to a two’s complement displacement d to point to an ...
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Z80 CPU User’s Manual 146 A ← Operation: Op Code: ADC Operands This s operand is any (HL), (IX+d), or (lY+d) as defined for the analogous ADD instruction. These possible ...
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Register Description: The s operand, along with the Carry Flag (C in the F register) is added to the contents of the Accumulator, and the result is stored in the Accumulator. Instruction ADC A, r ADC A, n ADC A, ...
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Z80 CPU User’s Manual 148 A ← Operation: Op Code: SUB Operands: s This s operand is any (HL), (IX+d), or (lY+d) as defined for the analogous ADD instruction. These possible Op Code/operand combinations ...
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Register Description: The s operand is subtracted from the contents of the Accumulator, and the result is stored in the Accumulator. Instruction SUB r SUB n SUB (HL) SUB (IX+d) SUB (lY+d) Condition Bits Affected set if result ...
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Z80 CPU User’s Manual 150 A ← Operation: Op Code: SBC Operands The s operand is any (HL), (IX+d), or (lY+d) as defined for the analogous ADD instructions. These possible ...
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assembled as follows in the object code field above: Register Description: The s operand, along with the Carry flag (C in the F register) is subtracted from the contents ...
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Z80 CPU User’s Manual 152 A ← A ∧ s Operation: Op Code: AND Operands: s The s operand is any (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible Op Code/operand combinations ...
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Register Description: A logical AND operation is performed between the byte specified by the s operand and the byte contained in the Accumulator; the result is stored in the Accumulator. Instruction AND r AND n AND (HL) AND (IX+d) AND ...
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Z80 CPU User’s Manual 154 A ← A ∨ s Operation: Op Code: OR Operands: s The s operand is any (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible Op Code/operand combinations ...
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Register Description: A logical OR operation is performed between the byte specified by the s operand and the byte contained in the Accumulator; the result is stored in the Accumulator. Instruction (HL) OR (IX+d) OR ...
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Z80 CPU User’s Manual 156 A ← A ⊕ s Operation: Op Code: XOR Operands: s The s operand is any (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible Op Code/operand combinations ...
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Register Description: The logical exclusive-OR operation is performed between the byte specified by the s operand and the byte contained in the Accumulator; the result is stored in the Accumulator. Instruction XOR r XOR n XOR (HL) XOR (IX+d) XOR ...
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Z80 CPU User’s Manual 158 Operation Code: CP Operands: s The s operand is any (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible Op Code/operand combinations are assembled ...
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Register Description: The contents of the s operand are compared with the contents of the Accumulator. If there is a true compare, the Z flag is set. The execution of this instruction does not affect the contents of the Accumulator. ...
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Z80 CPU User’s Manual 160 r ← Operation: Op Code: INC Operands Description: Register r is incremented and register r identifies any of the registers assembled as ...
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Operation: Op Code: INC Operands: (HL Description: The byte contained in the address specified by the contents of the HL register pair is incremented. M Cycles Condition Bits Affected set if ...
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Z80 CPU User’s Manual 162 (IX+d) ← (IX+ Operation: Op Code: INC Operands: (IX+ Description: The contents of the Index Register IX (register pair IX) are added to a two’s complement displacement integer d to point ...
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Operation: Op Code: INC Operands: (lY+ Description: The contents of the Index Register IY (register pair IY) are added to a two’s complement displacement integer d to point to an address ...
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Z80 CPU User’s Manual 164 m ← Operation: Op Code: DEC Operands: m The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous INC instructions. These possible Op Code/operand combinations are assembled ...
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Description: The byte specified by the m operand is decremented. Instruction DEC r DEC (HL) DEC (IX+d) DEC (lY+d) Condition Bits Affected set if result is negative; reset otherwise Z is set if result is zero; reset otherwise ...
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Z80 CPU User’s Manual 166 General-Purpose Arithmetic and CPU Control Operation: Op Code: DAA 0 Description: This instruction conditionally adjusts the Accumulator for BCD addition and subtraction operations. For addition ( , SBC DEC C Before Operation DAA 0 0 ...
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M Cycles Condition Bits Affected set if most-significant bit of Accumulator is 1 after operation; reset otherwise Z is set if Accumulator is zero after operation; reset otherwise H, see instruction P/V is set if Accumulator is even ...
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Z80 CPU User’s Manual 168 A ← A Operation: Op Code: CPL 0 Description: The contents of the Accumulator (register A) are inverted (one’s complement). Condition Bits Affected not affected Z is not affected H is set P/V ...
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A ← Operation: Op Code: NEG Description: The contents of the Accumulator are negated (two’s complement). This is the same as subtracting the contents of the Accumulator from zero. Note that 80H is ...
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Z80 CPU User’s Manual 170 CY ← CY Operation: Op Code: CCF 0 Description: The Carry flag in the F register is inverted. Condition Bits Affected not affected Z is not affected H, previous carry is copied P/V ...
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CY ← 1 Operation: Op Code: SCF 0 0 Description: The Carry flag in the F register is set. M Cycles Condition Bits Affected not affected Z is not affected H is reset P/V is not affected N ...
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Z80 CPU User’s Manual 172 Operation: — Op Code: NOP 0 Description: The CPU performs no operation during this machine cycle. Condition Bits Affected: None UM008005-0205 NOP Cycles T States ...
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Operation: — Op Code: HALT 0 1 Description: The HALT instruction suspends CPU operation until a subsequent interrupt or reset is received. While in the HALT state, the processor executes NOPs to maintain memory refresh logic. M Cycles Condition Bits ...
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Z80 CPU User’s Manual 174 IFF ← 0 Operation: Op Code Description: DI disables the maskable interrupt by resetting the interrupt enable flip- flops (IFF1 and IFF2). Note that this instruction disables the maskable interrupt during its execution. ...
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IFF ← 1 Operation: Op Code Description: The enable interrupt instruction sets both interrupt enable flip flops (IFFI and IFF2 logic 1, allowing recognition of any maskable interrupt. Note that during the execution of this ...
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Z80 CPU User’s Manual 176 Operation: — Op Code: IM Operands Description: The IM 0 instruction sets interrupt mode 0. In this mode, the interrupting device can insert any instruction on the data bus for execution by ...
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Operation: — Op Code: IM Operands Description: The IM 1 instruction sets interrupt mode 1. In this mode, the processor responds to an interrupt by executing a restart to location 0038H. M Cycles Condition Bits ...
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Z80 CPU User’s Manual 178 Operation: — Op Code: IM Operands Description: The IM 2 instruction sets the vectored interrupt mode 2. This mode allows an indirect call to any memory location by an 8-bit vector supplied ...
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Arithmetic Group HL ← Operation: Op Code: ADD Operands: HL Description: The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are added to the contents of register ...
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Z80 CPU User’s Manual 180 HL ← Operation: Op Code: ADC Operands: HL Description: The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are added with ...