CP82C54Z Intersil, CP82C54Z Datasheet - Page 7

• Manufacturer Part Number: CP82C54Z
• Description: IC TIMER PROG CMOS 8MHZ 24-PDIP
• Manufacturer: Intersil
• Type: Programmable Timerr

Specifications of CP82C54Z

• Frequency: 8MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The status register, shown in the figure, when latched,
contains the current contents of the Control Word Register
and status of the output and null count flag. (See detailed
explanation of the Read-Back command.)
The actual counter is labeled CE (for Counting Element). It is
a 16-bit presettable synchronous down counter.
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”; the subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally referred
to as one unit and called just OL. These latches normally
“follow” the CE, but if a suitable Counter Latch Command is
sent to the 82C54, the latches “latch” the present count until
read by the CPU and then return to “following” the CE. One
latch at a time is enabled by the counter’s Control Logic to drive
the internal bus. This is how the 16-bit Counter communicates
over the 8-bit internal bus. Note that the CE itself cannot be
read; whenever you read the count, it is the OL that is being
read.
Similarly, there are two 8-bit registers called CRM and CRL (for
“Count Register”). Both are normally referred to as one unit and
called just CR. When a new count is written to the Counter, the
count is stored in the CR and later transferred to the CE. The
Control Logic allows one register at a time to be loaded from
the internal bus. Both bytes are transferred to the CE
simultaneously. CRM and CRL are cleared when the Counter is
programmed for one byte counts (either most significant byte
only or least significant byte only) the other byte will be zero.
Note that the CE cannot be written into; whenever a count is
written, it is written into the CR.
The Control Logic is also shown in the diagram. CLK n,
GATE n, and OUT n are all connected to the outside world
through the Control Logic.
CLK n
REGISTER
CONTROL
CONTROL
FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM
GATE n
WORD
LOGIC
OUT n
REGISTER
STATUS
STATUS
LATCH
INTERNAL BUS
CR
OL
7
M
M
CE
CR
OL
L
L
82C54
82C54 System Interface
The 82C54 is treated by the system software as an array of
peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder.
Operational Description
General
After power-up, the state of the 82C54 is undefined. The
Mode, count value, and output of all Counters are undefined.
How each Counter operates is determined when it is
programmed. Each Counter must be programmed before it
can be used. Unused counters need not be programmed.
Programming the 82C54
Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word
specifies which Counter is being programmed.
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
Write Operations
The programming procedure for the 82C54 is very flexible.
Only two conventions need to be remembered:
1. For Each Counter, the Control Word must be written
2. The initial count must follow the count format specified in the
before the initial count is written.
Control Word (least significant byte only, most significant
byte only, or least significant byte and then most significant
byte).
FIGURE 4. COUNTER INTERNAL BLOCK DIAGRAM
OUT GATE CLK
A1
COUNTER
A1
A0
0
A0
CS
ADDRESS BUS (16)
CONTROL BUS
OUT GATE CLK
DATA BUS (8)
COUNTER
D0 - D7
82C54
1
8
OUT GATE CLK
COUNTER
RD
2
I/OR I/OW
WR