CP82C54-10 Intersil, CP82C54-10 Datasheet - Page 15

• Manufacturer Part Number: CP82C54-10
• Description: IC TIMER PROG CMOS 10MHZ 24-DIP
• Manufacturer: Intersil
• Type: Programmable Timerr

Specifications of CP82C54-10

• Frequency: 10MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Count: -

Counter will be loaded with new count on the next CLK pulse
and counting will continue from there.
Operation Common To All Modes
Programming
When a Control Word is written to a Counter, all Control
Logic, is immediately reset and OUT goes to a known initial
state; no CLK pulses are required for this.
Gate
The GATE input is always sampled on the rising edge of
CLK. In Modes 0, 2, 3 and 4 the GATE input is level
sensitive, and logic level is sampled on the rising edge of
CLK. In modes 1, 2, 3 and 5 the GATE input is rising-edge
sensitive. In these Modes, a rising edge of Gate (trigger)
sets an edge-sensitive flip-flop in the Counter. This flip-flop is
then sampled on the next rising edge of CLK. The flip-flop is
reset immediately after it is sampled. In this way, a trigger will
be detected no matter when it occurs - a high logic level
does not have to be maintained until the next rising edge of
CLK. Note that in Modes 2 and 3, the GATE input is both
edge-and level-sensitive.
GATE
GATE
GATE
OUT
OUT
OUT
CLK
CLK
CLK
WR
WR
WR
CW = 1A LSB = 3
CW = 1A LSB = 3
CW = 1A LSB = 3
N
N
N
N
N
N
N
N
N
FIGURE 14. MODE 5
N
N
N
N
N
N
LSB = 5
0
3
N
0
3
15
0
2
0
3
0
2
0
1
0
1
0
2
0
0
0
3
0
0
FF
FF
FF
FF
0
2
FF
FE
0
3
0
1
0
0
0
5
FF
FF
0
4
82C54
Counter
New counts are loaded and Counters are decremented on
the falling edge of CLK.
The largest possible initial count is 0; this is equivalent to 2
for binary counting and 10
The counter does not stop when it reaches zero. In Modes 0,
1, 4, and 5 the Counter “wraps around” to the highest count,
either FFFF hex for binary counting or 9999 for BCD
counting, and continues counting. Modes 2 and 3 are
periodic; the Counter reloads itself with the initial count and
continues counting from there.
NOTE: 0 is equivalent to 2
counting.
STATUS
SIGNAL
MODES
FIGURE 16. MINIMUM AND MAXIMUM INITIAL COUNTS
0
1
2
3
4
5
FIGURE 15. GATE PIN OPERATIONS SUMMARY
MODE
0
1
2
3
4
5
Disables Counting
1) Disables
counting
2) Sets output
immediately high
1) Disables
counting
2) Sets output
immediately high
1) Disables
Counting
GOING LOW
LOW OR
-
-
MIN COUNT
16
4
1) Initiates
Counting
2) Resets output
after next clock
Initiates Counting Enables Counting
Initiates Counting Enables Counting
Initiates Counting
for binary counting and 10
for BCD counting.
1
1
2
2
1
1
RISING
-
-
Enables Counting
Enables Counting
MAX COUNT
HIGH
0
0
0
0
0
0
4
-
-
for BCD
16