PCF8563TS/4,118 NXP Semiconductors, PCF8563TS/4,118 Datasheet

IC REAL TIME CLK/CALENDAR 8TSSOP

PCF8563TS/4,118

Manufacturer Part Number
PCF8563TS/4,118
Description
IC REAL TIME CLK/CALENDAR 8TSSOP
Manufacturer
NXP Semiconductors
Type
Clock/Calendarr
Datasheet

Specifications of PCF8563TS/4,118

Package / Case
8-TSSOP
Time Format
HH:MM:SS (24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Function
Clock/Calendar/Alarm/Timer Interrupt
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Rtc Bus Interface
Serial (2-Wire, I2C)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-3615 - DEMO BOARD I2C
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4517-2
935279522118
PCF8563TS-T
PCF8563TS-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCF8563TS/4,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features and benefits
3. Applications
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in
The PCF8563 is a CMOS
consumption. A programmable clock output, interrupt output, and voltage-low detector are
also provided. All addresses and data are transferred serially via a two-line bidirectional
I
automatically after each written or read data byte.
2
C-bus. Maximum bus speed is 400 kbit/s. The register address is incremented
PCF8563
Real-time clock/calendar
Rev. 8 — 18 November 2010
Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz quartz crystal
Century flag
Clock operating voltage: 1.0 V to 5.5 V at room temperature
Low backup current; typical 0.25 μA at V
400 kHz two-wire I
Programmable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz, and
1 Hz)
Alarm and timer functions
Integrated oscillator capacitor
Internal Power-On Reset (POR)
I
Open-drain interrupt pin
Mobile telephones
Portable instruments
Electronic metering
Battery powered products
2
C-bus slave address: read A3h and write A2h
2
C-bus interface (at V
1
Real-Time Clock (RTC) and calendar optimized for low power
DD
DD
= 1.8 V to 5.5 V)
= 3.0 V and T
Section
18.
amb
= 25 °C
Product data sheet

Related parts for PCF8563TS/4,118

PCF8563TS/4,118 Summary of contents

Page 1

PCF8563 Real-time clock/calendar Rev. 8 — 18 November 2010 1. General description The PCF8563 is a CMOS consumption. A programmable clock output, interrupt output, and voltage-low detector are also provided. All addresses and data are transferred serially via a two-line ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Type number PCF8563BS/4 PCF8563P/F4 PCF8563T/5 PCF8563T/F4 PCF8563TS/4 PCF8563TS/5 5. Marking Table 2. Type number PCF8563BS/4 PCF8563P/F4 PCF8563T/5 PCF8563T/F4 PCF8563TS/4 PCF8563TS/5 PCF8563 Product data sheet Ordering information Package Name Description HVSON10 plastic thermal enhanced very thin small outline package; no leads; 10 terminals; ...

Page 3

... NXP Semiconductors 6. Block diagram OSCI OSCILLATOR 32.768 kHz OSCO MONITOR (1) POWER ON RESET WATCH DOG 2 SDA I C-BUS INTERFACE SCL PCF8563 ( values see Table OSCO Fig 1. Block diagram of PCF8563 PCF8563 Product data sheet DIVIDER CONTROL 00 CONTROL_STATUS_1 01 CONTROL_STATUS_2 0D CLKOUT_CONTROL TIME 02 VL_SECONDS 03 MINUTES 04 HOURS 05 DAYS ...

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... NXP Semiconductors 7. Pinning information 7.1 Pinning terminal 1 index area OSCO Fig 2. OSCO Fig 4. PCF8563 Product data sheet 1 10 OSCI n. PCF8563BS n. CLKOUT INT 4 7 SCL SDA SS 001aaf981 Transparent top view For mechanical details, see Figure 30 Pin configuration for HVSON10 (PCF8563BS OSCI V DD ...

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... NXP Semiconductors 7.2 Pin description Table 3. Symbol OSCI OSCO INT V SS SDA SCL CLKOUT V DD n.c. [1] The die paddle (exposed pad) is wired Functional description The PCF8563 contains sixteen 8-bit registers with an auto-incrementing register address, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which ...

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... NXP Semiconductors 8.2 Register organization Table 4. Formatted registers overview Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they could be either logic 0 or logic 1. After reset, all registers are set according to Address Register name ...

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... NXP Semiconductors 8.3 Control registers 8.3.1 Register Control_status_1 Table 5. Control_status_1 - control and status register 1 (address 00h) bit description Bit Symbol Value Description [1] 7 TEST1 0 normal mode 1 EXT_CLK test mode [ unused [1] 5 STOP 0 RTC source clock runs 1 all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (CLKOUT at 32 ...

Page 8

... NXP Semiconductors 8.3.2.1 Interrupt output Bits TF and AF: timer countdown set to logic 1. These bits maintain their value until overwritten using the interface. If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another, a logic AND is performed during a write access ...

Page 9

... NXP Semiconductors 8.4 Time and date registers The majority of the registers are coded in the BCD format to simplify application use. 8.4.1 Register VL_seconds Table 8. Bit Symbol SECONDS [1] Start-up value. Table 9. Seconds value (decimal 8.4.1.1 Voltage-low detector and clock monitor The PCF8563 has an on-chip voltage-low detector (see ...

Page 10

... NXP Semiconductors The VL flag is intended to detect the situation when V under battery operation. Should the oscillator stop or V re-asserted, then the VL flag is set. This will indicate that the time may be corrupted. 8.4.2 Register Minutes Table 10. Bit Symbol MINUTES 8.4.3 Register Hours Table 11. ...

Page 11

... NXP Semiconductors Table 14. [1] Day Sunday Monday Tuesday Wednesday Thursday Friday Saturday [1] Definition may be re-assigned by the user. 8.4.6 Register Century_months Table 15. Bit Symbol MONTHS [1] This bit may be re-assigned by the user. [2] This bit is toggled when the register Years overflows from 99 to 00. ...

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... NXP Semiconductors 8.4.7 Register Years Table 17. Bit Symbol YEARS [1] When the register Years overflows from 99 to 00, the century bit C in the register Century_months is toggled. 8.5 Setting and reading the time Figure 8 Fig 8. During read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked ...

Page 13

... NXP Semiconductors Fig consequence of this method very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. Failing to comply with this method could result in the time becoming corrupted example, if the time (seconds through to hours) is set in one access and then in a second access the date is set possible that the time may increment between the two accesses ...

Page 14

... NXP Semiconductors 8.6 Alarm registers 8.6.1 Register Minute_alarm Table 18. Bit Symbol 7 AE_M MINUTE_ALARM [1] Default value. 8.6.2 Register Hour_alarm Table 19. Bit Symbol 7 AE_H HOUR_ALARM [1] Default value. 8.6.3 Register Day_alarm Table 20. Bit Symbol 7 AE_D DAY_ALARM [1] Default value. 8.6.4 Register Weekday_alarm Table 21. Bit Symbol ...

Page 15

... NXP Semiconductors 8.6.5 Alarm flag By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the corresponding alarm condition(s) are active. When an alarm occurs set to logic 1. The asserted AF can be used to generate an interrupt (INT). The AF is cleared using the interface. The registers at addresses 09h through 0Ch contain alarm information. When one or ...

Page 16

... NXP Semiconductors Table 22. Bit Symbol FD[1:0] [1] Default value. 8.8 Timer function The 8-bit countdown timer at address 0Fh is controlled by the Timer_control register at address 0Eh. The Timer_control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or counts down from a software-loaded 8-bit binary value. At the end of every countdown, the timer sets the timer flag TF ...

Page 17

... NXP Semiconductors 8.8.2 Register Timer Table 24. Bit Table 25. Bit 7 128 The register Timer is an 8-bit binary countdown timer enabled and disabled via the Timer_control register bit TE. The source clock for the timer is also selected by the Timer_control register. Other timer properties such as interrupt generation are controlled ...

Page 18

... NXP Semiconductors 5. Apply 32 clock pulses to CLKOUT. 6. Read time registers to see the first change. 7. Apply 64 clock pulses to CLKOUT. 8. Read time registers to see the second change. Repeat steps 7 and 8 for additional increments. 8.10 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP ...

Page 19

... NXP Semiconductors Table 26. First increment of time circuits after STOP bit release Bit Prescaler bits STOP Clock is running normally 0 01-0 0001 1101 0100 STOP bit is activated by user XX-0 0000 0000 0000 New time is set by user 1 XX-0 0000 0000 0000 STOP bit is released by user ...

Page 20

... NXP Semiconductors Table 27. Address Register name 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh [1] Registers marked x are undefined at power-up and unchanged by subsequent resets. 8.11.1 Power-On Reset (POR) override The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device ...

Page 21

... NXP Semiconductors 9. Characteristics of the I 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy ...

Page 22

... NXP Semiconductors SDA SCL MASTER TRANSMITTER RECEIVER Fig 16. System configuration 9.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • ...

Page 23

... NXP Semiconductors 2 9.5 I C-bus protocol 9.5.1 Addressing Before any data is transmitted on the I addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line ...

Page 24

... NXP Semiconductors acknowledgement from slave S SLAVE ADDRESS 0 A R/W (1) At this moment master transmitter becomes master receiver and PCF8563 slave receiver becomes slave transmitter. Fig 20. Master reads after setting register address (write register address; READ data) Fig 21. Master reads slave immediately after first byte (READ mode) ...

Page 25

... NXP Semiconductors 9.6 Interface watchdog timer WD timer counters a. Correct data transfer: read or write WD timer counters b. Incorrect data transfer; read or write Fig 22. Interface watchdog timer During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface, the PCF8563 has a built in watchdog timer ...

Page 26

... NXP Semiconductors 10. Internal circuitry Fig 23. Device diode protection diagram PCF8563 Product data sheet OSCI OSCO INT V SS PCF8563 All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2010 PCF8563 Real-time clock/calendar V DD CLKOUT SCL SDA 013aaa348 © NXP B.V. 2010. All rights reserved. ...

Page 27

... NXP Semiconductors 11. Limiting values Table 28. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I supply current DD V input voltage I V output voltage O I input current I I output current O P total power dissipation tot V electrostatic discharge voltage ...

Page 28

... NXP Semiconductors 12. Static characteristics Table 29. Static characteristics specified. Symbol Parameter Supplies V supply voltage DD I supply current DD Inputs V LOW-level input IL voltage V HIGH-level IH input voltage I input leakage LI current C input i capacitance PCF8563 Product data sheet − ° ° + 32.768 kHz; quartz R amb osc Conditions interface inactive ...

Page 29

... NXP Semiconductors Table 29. Static characteristics specified. Symbol Parameter Outputs I LOW-level OL output current I output leakage LO current Voltage detector V low voltage low [1] For reliable oscillator start-up at power-up: V ⁄ 1 [2] Timer source clock = Hz, level of pins SCL and SDA [3] Tested on sample basis (μA) 0.8 ...

Page 30

... NXP Semiconductors (μA) 0.8 0.6 0.4 0.2 0 − Timer = 1 minute. DD Fig 26. Supply current function of DD temperature T; CLKOUT = 32 kHz PCF8563 Product data sheet mgr890 4 frequency deviation (ppm −2 − 120 T (°C) T Fig 27. Frequency deviation as a function of supply voltage V All information provided in this document is subject to legal disclaimers. ...

Page 31

... NXP Semiconductors 13. Dynamic characteristics Table 30. Dynamic characteristics specified. Symbol Parameter Oscillator C capacitance on pin OSCO OSCO Δf /f relative oscillator frequency variation osc osc Quartz crystal parameters (f = 32.768 kHz) R series resistance s C load capacitance L C trimmer capacitance trim CLKOUT output δ duty cycle on pin CLKOUT ...

Page 32

... NXP Semiconductors SDA SCL SDA Fig 28. I 14. Application information Fig 29. Application diagram PCF8563 Product data sheet t t BUF LOW t HD;STA C-bus timing waveforms 1 F 100 CLOCK CALENDAR OSCI PCF8563 OSCO V SS All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2010 ...

Page 33

... NXP Semiconductors 14.1 Quartz frequency adjustment 14.1.1 Method 1: fixed OSCI capacitor By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. The frequency is best measured via the 32.768 kHz signal available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average ± ...

Page 34

... NXP Semiconductors 15. Package outline HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 0. terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 35

... NXP Semiconductors DIP8: plastic dual in-line package; 8 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 36

... NXP Semiconductors SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 37

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 38

... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...

Page 39

... NXP Semiconductors 17.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17 ...

Page 40

... NXP Semiconductors Fig 34. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 33. Acronym BCD CDM CMOS ESD HBM LSB MSB MSL PCB POR RTC SCL SDA ...

Page 41

... NXP Semiconductors 19. References [1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [5] JESD22-A114 — ...

Page 42

... NXP Semiconductors 20. Revision history Table 34. Revision history Document ID Release date PCF8563 v.8 20101118 • Modifications: Added new product types PCF8563 v.7 20100723 PCF8563_6 20080221 PCF8563_5 20070717 PCF8563-04 20040312 (9397 750 12999) PCF8563-03 20030414 (9397 750 11158) PCF8563-02 19990416 (9397 750 04855) ...

Page 43

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 44

... For sales office addresses, please send an email to: PCF8563 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 45

... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 5 8.1 CLKOUT output . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 Register organization . . . . . . . . . . . . . . . . . . . . 6 8.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3.1 Register Control_status_1 . . . . . . . . . . . . . . . . 7 8 ...

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