M41ST87WMX6 STMicroelectronics, M41ST87WMX6 Datasheet
M41ST87WMX6
Specifications of M41ST87WMX6
M41ST87WMX6
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M41ST87WMX6 Summary of contents
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V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM Features ■ 5.0, 3.3, or 3.0 V operation 2 ■ 400 kHz I C bus ■ NVRAM supervisor to non-volatize ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41ST87Y, M41ST87W 3.1 TIMEKEEPER 3.2 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41ST87Y, M41ST87W List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The M41ST87Y/W secure serial RTC and NVRAM supervisor is a low power 1280-bit, static CMOS SRAM organized as 160 bytes by 8 bits. A built-in 32.768 kHz oscillator (internal crystal-controlled) and 8 bytes of the SRAM are ...
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M41ST87Y, M41ST87W Figure 1. Logic diagram 1. Open drain output. 2. Programmable output (open drain or full-CMOS). Defaults to open drain on first power-up. 3. Available in SOX28 (MX) package only. 4. Available in SSOP (SS) package only. V BAT ...
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Description Figure 2. 28-pin, 300 mil SOIC (MX) connections Note: No function (NF) and no connect (NC) pins should be tied to V internally shorted together. Figure 3. 20-pin, SSOP (SS) connections Note: No connect (NC) pin should be tied ...
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M41ST87Y, M41ST87W Table 1. Signal names (1) XI (1) XO (2) E CON (2) EX (3) IRQ/OUT PFI 1 PFI 2 (4) PFO 1 (4) PFO 2 (3) RST RSTIN1 (2) RSTIN2 SCL SDA (4) SQW/FT (2) WDI V CC ...
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Description Figure 4. Block diagram SDA INTERFACE SCL (4) Crystal XI OSCILLATOR V OUT XO (3) WDI 2 TPX BAT V SS RSTIN1 (3) RSTIN2 (3) EX PFI 1 1.25V (Internal) PFI 2 1.25V (Internal) 1. ...
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M41ST87Y, M41ST87W Figure 5. Hardware hookup Unregulated V Voltage IN 5V Regulator V IN 3.3V Regulator For monitoring of additional voltage sources Pushbutton Available in SOX28 (MX) package only. M41ST87Y TP1 ...
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Operating modes 2 Operating modes The M41ST87Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 160 bytes contained in the device can ...
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M41ST87Y, M41ST87W 2.1 2-wire bus characteristics The bus is intended for communication between different ICs. It consists of two lines: a clock signal (SCL) and a bidirectional data signal (SDA). The SDA line must be connected to a positive supply ...
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Operating modes case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 6. Serial bus data transfer sequence CLOCK DATA START CONDITION Figure 7. Acknowledgement sequence START SCL FROM MASTER DATA ...
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M41ST87Y, M41ST87W Table 2. AC characteristics Symbol f SCL clock frequency SCL t Time the bus must be free before a new transmission can start BUF ( propagation delay EXPD CON t SDA and SCL fall ...
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Operating modes Figure 9. Slave address location START Figure 10. READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X Figure 11. Alternate READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ...
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M41ST87Y, M41ST87W 2.3 WRITE mode In this mode the master transmitter transmits to the M41ST87Y/W slave receiver. Bus protocol is shown in (R placed on the bus and indicates to the addressed device that word address An ...
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Operating modes power input is switched from the V SRAM are maintained from the attached battery supply. All signal outputs become high impedance. The V current to the attached memory with less than 0.3 volts drop under this condition. On ...
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M41ST87Y, M41ST87W 2.6.2 Tamper bits (TB1 and TB2) If the TEB bit is set, and a tamper condition occurs, the TB X “Read-only” and is reset only by setting the TEB register 0Fh. 2.6.3 Tamper interrupt enable bits (TIE1 and ...
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Operating modes Figure 14. Tamper detect connection options I. NORMALLY OPEN (TCM III. V OUT ( NORMALLY TCHI/TCLO = 1 CLOSED (TCM Note: These options are summarized the CLRX ...
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M41ST87Y, M41ST87W Figure 15. Basic tamper detect options OUT TCM , TPM = 1 OUT TCM , TPM = 0 TCM , TPM = 1 TCM , TPM ...
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Operating modes 2.6.6 Tamper detect sampling (TDS1 and TDS2) This bit selects between a 1Hz sampling rate or constant monitoring of the tamper input pin(s) to detect a tamper event when the normally closed switch mode is selected. This allows ...
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M41ST87Y, M41ST87W negative voltage generated by the charge pump during a tamper condition, and from being pulled to ground by the output of the charge pump when shut-down mode (SHDN = logic low). The gates of both ...
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Operating modes Figure 18. Tamper current options OUT TAMPER HI, NORMALLY OPEN OUT TAMPER LO, TCHI/TCLO = 1 NORMALLY CLOSED TAMPER LO, NORMALLY OPEN TCHI/TCLO = 1 TAMPER HI, NORMALLY CLOSED Figure ...
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M41ST87Y, M41ST87W Table 5. Tamper detect timing Symbol Parameter (1) t Tamper RAM clear ext delay CLRD t Tamper clear timing CLR 1. With input capacitance = 70 pF and resistance = 50 Ω the OF bit is ...
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Operating modes 2.7 Tamper detection operation The tamper pins are triggered based on the state of an external switch. Two switch mode options are available, normally open or normally closed, based on the setting of the tamper connect mode bit ...
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M41ST87Y, M41ST87W 2.9 Internal tamper pull-up/down current Depending on the capacitive and resistive loading of the tamper pin input (TP may require more or less current from the internal pull-up/down used when monitoring the normally closed switch mode. The state ...
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Operating modes 2.11 Tamper event time-stamp Regardless of which tamper occurs first, not only will the appropriate tamper bit be set, but the event will also be automatically time-stamped. This is accomplished by freezing the normal update of the clock ...
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M41ST87Y, M41ST87W 3 Clock operation The eight byte clock register (see read the date and time from the clock binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Note: ...
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Clock operation 3.1 TIMEKEEPER The M41ST87Y/W offers 22 internal registers which contain clock, control, alarm, watchdog, flag, square wave, and tamper data. The 8 clock registers are memory locations which contain external (user accessible) and internal copies of the data ...
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M41ST87Y, M41ST87W Keys Must be set to zero 32kE = 32 kHz output enable bit ABE = Alarm in battery backup mode enable bit RS0-RS3 = SQW frequency AF = Alarm flag (read only) AFE = Alarm flag ...
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Clock operation Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that ...
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M41ST87Y, M41ST87W Figure 22. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 –20 Figure 23. Calibration waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 3.3 Setting alarm clock registers Address locations 0Ah-0Eh ...
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Clock operation alarm condition activates the IRQ/OUT pin as shown in alarm, write '0' to the alarm date register and to RPT5–RPT1. If the address pointer is allowed to increment to the flag register address, an alarm condition will not ...
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M41ST87Y, M41ST87W Figure 25. Backup mode alarm waveform PFD V SO ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/OUT 3.4 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. ...
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Clock operation Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, either a transition of the WDI pin value of 00h needs to be written to the watchdog register in order to ...
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M41ST87Y, M41ST87W 3.6 Full-time 32 kHz square wave output The M41ST87Y/W offers the user a special 32 kHz square wave function which defaults to output on the F 32k (ST bit = '0'). This function is available within one second ...
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Clock operation Table 10. Reset AC characteristics Symbol (2) t RSTIN1 low to RST low (min pulse width) R1 (2) t RSTIN2 low to RSTIN2 high (min pulse width) R2 (3) t RSTIN1 or RSTIN2 high to RST high rec ...
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M41ST87Y, M41ST87W 3.11 Century bits These two bits will increment in a binary fashion at the turn of the century, and handle leap years correctly. Refer to years register (07h), and should be set accordingly. For example, for the year ...
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Clock operation The M41ST87Y/W only monitors the battery when a nominal V Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be ...
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M41ST87Y, M41ST87W 3.17 Initial power-on defaults Table 13. Default values Condition Initial power-up Subsequent power-up (with (2)(3) battery backup) Condition Initial power-up Subsequent power-up (with (2)(3) battery backup) Condition Initial power-up Subsequent power-up (with (2) battery backup) TCHI/TCLO1 Condition Initial ...
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Maximum ratings 4 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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M41ST87Y, M41ST87W 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests ...
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DC and AC parameters Table 17. DC characteristics Sym Parameter Test condition Battery current OSC ° (2) I BAT Battery current OSC OFF I Supply current CC1 Supply current SCL, SDA ≥ ...
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... S C Load capacitance L 1. User supplied for the 20-lead SSOP package. STMicroelectronics recommends the KDS DT- mm) for thru-hole, or the KDS DMX-26S (3 mm) for surface-mount, tuning fork-type quartz crystals. For contact information, see References on page 52. 2. Load capacitors are integrated within the M41ST87. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account ...
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DC and AC parameters Figure 28. Power down/up mode AC waveforms PFD (max) V PFD (min PFO VALID INPUTS RECOGNIZED RST OUTPUTS VALID (PER CONTROL INPUT) (1) E CON 1. E ...
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M41ST87Y, M41ST87W 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ...
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Package mechanical data Figure 30. SSOP20 – 20-lead, shrink, small outline package outline Table 21. SSOP20 – 20-lead, shrink, small outline package mechanical data Sym A A1 0.050 A2 1.650 b 0.220 c 0.090 D 6.900 E 7.400 E1 5.000 ...
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M41ST87Y, M41ST87W Figure 31. Carrier tape for SOX28 package T TOP COVER TAPE K 0 Table 22. Carrier tape dimensions for SOX28 package Package 1.50 24.00 1.75 SOX28 +0.10/ ±0.30 ±0.10 –0.00 Figure 32. Carrier tape for ...
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Package mechanical data Figure 33. Reel schematic D A Full radius Table 23. Reel dimensions for 24 mm carrier tape (SOX28 package) and 16 mm carrier tape (SSOP20 package) A Carrier tape (max) 330 (SOX28) (13-inch) 330 ...
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M41ST87Y, M41ST87W 7 Part numbering Table 24. Ordering information scheme Example: Device type M41ST Supply voltage and write protect voltage (1) 87Y = V = 4. THS bit = '1': 4.50 V ≤ ...
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References 8 References KDS, the crystal component supplier mentioned in this document, can be contacted at kouhou@kdsj.co.jp or http://www.kds.info/index_en.htm 52/54 Doc ID 9497 Rev 9 M41ST87Y, M41ST87W ...
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M41ST87Y, M41ST87W 9 Revision history Table 25. Document revision history Date Revision May-2002 23-Apr-2003 10-Jul-2003 11-Sep-2003 15-Jun-2004 7-Sep-2004 29-Jun-2005 28-Mar-2006 10-Sep-2008 31-Mar-2010 25-Jan-2011 1 First issue. 2 Document promoted to preliminary data. 2.1 Update tamper information ( Update electrical, charge ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...