DS1743-100IND+ Maxim Integrated Products, DS1743-100IND+ Datasheet

IC RTC RAM Y2K 5V 100NS 28-EDIP

DS1743-100IND+

Manufacturer Part Number
DS1743-100IND+
Description
IC RTC RAM Y2K 5V 100NS 28-EDIP
Manufacturer
Maxim Integrated Products
Type
Clock/Calendar/NVSRAM/Y2Kr
Datasheet

Specifications of DS1743-100IND+

Memory Size
64K (8K x 8)
Time Format
HH:MM:SS (24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
28-DIP Module (600 mil), 28-EDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
FEATURES
 Integrated NV SRAM, Real-Time Clock,
 Clock Registers are Accessed Identically to
 Century Byte Register
 Totally Nonvolatile with Over 10 Years of
 BCD-Coded Century, Year, Month, Date,
 Low-Battery-Voltage Level Indicator Flag
 Power-Fail Write Protection Allows for ±10%
 Lithium Energy Source is Electrically
 DIP Module Only
 PowerCap Module Board Only
Crystal, Power-Fail Control Circuit, and
Lithium Energy Source
the Static RAM. These Registers Reside in
the Eight Top RAM Locations.
Operation in the Absence of Power
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
through 2099
V
Disconnected to Retain Freshness Until
Power is Applied for the First Time
Standard JEDEC Bytewide 8k x 8 Static
Surface-Mountable Package for Direct
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
Underwriters Laboratories (UL) Recognized
to Prevent Charging of the Internal Lithium
Battery
CC
RAM Pinout
Connection to PowerCap Containing
Battery and Crystal
of DS174XP Timekeeping RAM
Power-Supply Tolerance
Y2K-Compliant, Nonvolatile Timekeeping
1 of 16
PIN CONFIGURATIONS
TOP VIEW
GND
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
N.C.
N.C.
N.C.
RST
V
WE
OE
CE
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GND
N.C.
DQ0
DQ1
DQ2
34-Pin PowerCap Module Board
A12
(Uses DS9034PCX PowerCap)
28-Pin Encapsulated Package
A7
A6
A5
A4
A3
A2
A1
A0
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(28 PIN 740)
DS1743/DS1743P
GND
DS1743P
DS1743
V
BAT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
X2
V
WE
CE2
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
CC
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
REV
RAMs
: 090407
N.C.
N.C.
N.C.
N.C.
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

Related parts for DS1743-100IND+

DS1743-100IND+ Summary of contents

Page 1

... CE2 A11 A10 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 28-Pin Encapsulated Package (28 PIN 740 DS1743P GND BAT 34-Pin PowerCap Module Board (Uses DS9034PCX PowerCap) : 090407 REV N.C. N.C. N.C. N.C. A12 A11 A10 A9 A8 ...

Page 2

... DQ0 12 15 DQ1 13 14 DQ2 14 17 GND 15 13 DQ3 16 12 DQ4 17 11 DQ5 18 10 DQ6 19 9 DQ7 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs FUNCTION PDIP No Connection Address Input Data Input/ Output — Ground — Data Input/ — Output PIN NAME FUNCTION PowerCap ...

Page 3

... The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1743 also contains its own power- fail circuitry, which deselects the device when the V ...

Page 4

... CLOCK OPERATIONS-READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. ...

Page 5

... As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit like the read bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time data in 24-hour BCD format. Resetting the write bit then transfers those values to the actual clock counters and allows normal operation to resume ...

Page 6

... Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation. RETRIEVING DATA FROM RAM OR CLOCK The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM ...

Page 7

... WRITING DATA TO RAM OR CLOCK The DS1743 is in the write mode whenever WE, and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout the cycle must return inactive for a minimum of t cycle. Data in must be valid t application, the OE signal will be high during a write cycle ...

Page 8

... Output Leakage Current (Any Output) Output Logic 1 Voltage (I = -1.0mA) OUT Output Logic 0 Voltage (I = 2.1mA) OUT Write-Protection Voltage Battery Switchover Voltage DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs TEMP RANGE 3.3V 10 10% 0°C to +70°C 3.3V 10 10% -40C to +85C SYMBOL CONDITIONS = 5V 10 ...

Page 9

... Over the Operating Range PARAMETER SYMBOL Read Cycle Time Address Access Time CE to CE2 to DQ Low-Z CE Access Time CE2 Access Time CE and CE2 Data-Off Time Low-Z OE Access Time OE Data-Off Time Output Hold from Address DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN CC1 I CC2 ...

Page 10

... Address Access Time CE and CE2 Low to DQ Low-Z CE and CE2 Access Time CE and CE2 Data-Off time OE Low to DQ Low-Z OE Access Time OE Data-Off Time Output Hold from Address READ CYCLE TIMING DIAGRAM DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ACCESS 120ns SYMBOL MIN MAX MIN t 120 ...

Page 11

... PARAMETER Write Cycle Time Address Setup Time WE Pulse Width CE and CE2 Pulse Width Data Setup Time Data Hold Time CE Data Hold Time CE2 Address Hold Time WE Data-Off Time Write Recovery Time DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ACCESS 70ns MIN MAX MIN ...

Page 12

... WRITE CYCLE TIMING—WRITE-ENABLE CONTROLLED (See Note 5) WRITE CYCLE TIMING— CE /CE2-CONTROLLED (See Note 5) DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ...

Page 13

... CE2 Before IH IL Power-Down V Fall Time PF(MAX) PF(MIN) V Fall Time PF(MIN Rise Time PF(MIN) PF(MAX) Power-Up Recover Time Expected Data-Retention Time (Oscillator On) POWER-UP/DOWN TIMING (5V DEVICE) DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP 300 REC MAX UNITS NOTES s s s  ...

Page 14

... PF(MIN) V Rise Time PF(MIN) PF(MAX) to RST High V PF Expected Data-Retention Time (Oscillator On) POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE) CAPACITANCE (T = +25C) A PARAMETER Capacitance on All Input Pins Capacitance on All Output Pins DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP 300 REC SYMBOL MIN ...

Page 15

... If CE2 is used to terminate a write, the CE2 data hold time (t 6) Data-retention time is at +25C. 7) Each DS1743 has a built-in switch that disconnects the lithium source until V user. The expected t is defined for DIP modules as a cumulative time in the absence from the time power is first applied by the user ...

Page 16

... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor. DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs DOCUMENT NO. 21-0245 ...

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