DS14285 Maxim Integrated Products, DS14285 Datasheet
DS14285
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DS14285 Summary of contents
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... FEATURES Direct Replacement for IBM AT Computer Clock/Calendar Functionally Compatible with the DS1285/DS1287 Available as Chip (DS14285, DS14285S, or DS14285Q) or Stand-Alone Module with Embedded Lithium Battery and Crystal (DS14287) Automatic Backup Supply and Write Protection to Make External SRAM Nonvolatile Counts Seconds, Minutes, Hours, Days, ...
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... Denotes a lead-free/RoHS-compliant device “+” anywhere on the top mark denotes a lead-free/RoHS-compliant device. An “N” denotes an industrial temperature grade device. PIN DESCRIPTION AD0-AD7 - Multiplexed Address/Data Bus Connection MOT - Bus Type Select (DS14285Q only) - Chip Select Address Strobe R/ - Read/Write Input W DS ...
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... AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or pulses read cycle the DS14285/DS14287 outputs 8 bits of data during the latter portion of the DS or pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions ...
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... Strobe. During read cycles, DS signifies the time that the DS14285Q is to drive the bidirectional bus. In write cycles the trailing edge of DS causes the DS14285Q to latch the written data. When the MOT pin is connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read( the time period when the DS14285Q drives the bus with read data ...
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... RESET time is low should exceed 200 ms to make sure that the internal timer that controls the RESET DS14285/DS14287 on power-up has timed out. When following occurs: A. Periodic Interrupt Enable (PEI) bit is cleared Alarm Interrupt Enable (AIE) bit is cleared Update Ended Interrupt Flag (UF) bit is cleared to 0. ...
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... The battery should be connected directly to the V battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current protection circuitry is provided internal to the device and has passed the requirements of Underwriters Laboratories for UL listing. Figure 1. DS14285/DS14287 Block Diagram pin. A diode must not be placed in series with the BAT ...
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... When the device is in battery backup mode, the energy source connected to the V the DS14285, or the internal lithium cell in the case of the DS14287 can power an external SRAM for an extended period of time. The amount of time that the lithium cell can supply power to the external SRAM is a function of the data retention current of the SRAM ...
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... RTC ADDRESS MAP The address map of the DS14285/DS14287 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which are used for control and status. All 128 bytes can be directly written or read except for the following: 1 ...
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When the 12-hour format is selected, the high order bit of the hours byte represents PM when logic one. The time, calendar, and alarm bytes are always ...
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... CONTROL REGISTERS The DS14285/DS14287 has four control registers that are accessible at all times, even during the update cycle. REGISTER A MSB BIT 7 BIT 6 UIP DV2 UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit the update transfer will soon occur. When UIP the update transfer will not occur for at least 244 µ ...
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... IRQ PIE bit blocks the output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is IRQ still set at the periodic rate. PIE is not modified by any internal DS14285/DS14287 functions, but is cleared RESET AIE - The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set permits the Alarm Flag (AF) bit in register C to assert equal the 3 alarm bytes including a “ ...
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... VRT - The Valid RAM and Time (VRT) bit indicates the condition of the internal battery (the battery connected to the V pin in the case of the DS14285S, DS14285, and the DS14285Q). This bit is not BAT writable and should always when read ever present, an exhausted internal lithium energy source is indicated and both the contents of the RTC data and RAM data are questionable ...
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... The DS14285/DS14287 can also provide additional nonvolatile RAM. This is accomplished through the use of its internal lithium cell in the case of the DS14287 (or the energy source connected to the V in the case of the DS14285) and battery-backup controller to make a standard CMOS SRAM nonvolatile during power-fail conditions. During power-fail, the DS14285/DS14287 automatically write-protects the external SRAM and provides a V the DS14285/DS14287 and an external SRAM is illustrated in Figure 3 ...
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... Determination that the RTC initiated an interrupt is IRQ accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts have been initiated by the DS14285/DS14287. The act of reading Register C clears all active flag bits and the IRQF bit. PERIODIC INTERRUPT SELECTION The periodic interrupt will cause the every 122 µ ...
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... UPDATE CYCLE The DS14285/DS14287 executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time increments. However, the time countdown chain continues to update the internal copy of the buffer ...
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Figure 4. Update-Ended and Periodic Interrupt Relationship ...
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ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +7.0V Storage Temperature Range………………………………………………………………...-40°C to +85°C Soldering Temperature: DIP…………………………………………..260°C for 10 seconds (See Note 12) Soldering Temperature: Surface Mount:…………………………….See IPC/JEDEC Standard J-STD-020 This is a stress rating only ...
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AC ELECTRICAL CHARACTERISTICS (Over the operating range) PARAMETER Cycle Pulse Width, DS/E Low or RD/ High Pulse Width, DS/E Low or RD/ Low Input Rise and Fall Time R/ Hold Time W R/ Setup Time Before DS/E W Chip Select ...
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... Figure 5. Output Load DS14285 BUS TIMING FOR MOTOROLA INTERFACE ...
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... DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE WRITE CYCLE ...
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... DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE READ CYCLE DS14285/DS14287 IRQ RELEASE DELAY TIMING ...
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POWER-DOWN/POWER-UP TIMING POWER-DOWN/POWER-UP TIMING PARAMETER at V before Power-Down slew from 4. slew from after Power- Chip-Enable Propagation Delay to External ...
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NOTES: 1) All voltages are referenced to ground. 2) All outputs are open. 3) The MOT pin has an internal pulldown of 20kΩ. 4) The pin has an internal pullup of 50kΩ. CEI 5) Applies to the AD0–AD7 pins, the ...
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... PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) DS14285 24-PIN DIP DS14285 24-PIN SO PKG 24-PIN DIM MIN MAX A IN. 1.245 1.270 MM 31.62 32.25 B IN. 0.530 0.550 MM 13.46 13 ...
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... PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) DS14285Q 28-PIN PLCC PKG DIM CH1 28-PIN MIN MAX 0.165 0.180 0.090 0.120 0.020 - 0.026 0.033 0.013 0.021 ...
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... The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. NOTE: PINS 2, 3, 16, AND 20 ARE MISSING BY DESIGN. 24-PIN MAX 1.335 33.91 0.740 18.80 0.370 9.40 0.130 3.30 0.030 0.76 0.140 3.56 0.110 2.79 0.630 16.00 0.012 0.30 0.021 0. © 2005 Maxim Integrated Products • Printed USA DS14285/DS14287 ...