MCP3901T-I/SS Microchip Technology, MCP3901T-I/SS Datasheet
MCP3901T-I/SS
Specifications of MCP3901T-I/SS
Related parts for MCP3901T-I/SS
MCP3901T-I/SS Summary of contents
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... Energy Metering and Power Measurement • Automotive • Portable Instrumentation • Medical and Power Monitoring © 2010 Microchip Technology Inc. Description The MCP3901 is a dual channel Analog Front End (AFE) containing two synchronous sampling Delta- Sigma Analog-to-Digital Converters (ADC), two PGAs, ...
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... Shifter DATA_CH1<23:0> Δ -Σ 3 SINC Modulator SDN<1:0>, RESET<1:0>, GAIN<7:0> MOD<7:0> POR AGND DGND Xtal Oscillator OSC1 MCLK Clock Generation OSC2 OSR<1:0> DMCLK PRE<1:0> DR SDO Digital SPI RESET Interface SDI SCK CS MODOUT<1:0> Modulator MDAT0 Output Block MDAT1 © 2010 Microchip Technology Inc. ...
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... BOOST bits off. With BOOST bits on, AMCLK should be in the range 8.192 MHz, AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to ‘0’. © 2010 Microchip Technology Inc. † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device ...
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... From -40°C to +125° All Gains ppm/°C From -40°C to +125°C ppm GAIN = 1, DITHER = On kΩ Proportional to 1/AMCLK dB OSR = 256, DITHER = OSR = 256, DITHER = OSR = 256, DITHER = OSR = 256, DITHER = OSR = 256, DITHER = On Figure 2-19 for typical values). © 2010 Microchip Technology Inc. ...
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... For proper operation and to keep ADC accuracy, AMCLK should always be in the range MHz with BOOST bits off. With BOOST bits on, AMCLK should be in the range 8.192 MHz, AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to ‘0’. © 2010 Microchip Technology Inc. = 4.5 to 5.5V ...
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... V SDO pin only +2 and MDAT pins only +800 mA 5. SDO pin only -2 and MDAT pins only -800 µ 5. µ DGND µ DGND or DV OUT 25°C, A SCK = 1.0 MHz 5.0V (Note 1) DD © 2010 Microchip Technology Inc. ...
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... Serial Output Timing Diagram CSS Mode 1,1 Mode 0,0 SCK SDI MSB In SDO FIGURE 1-2: Serial Input Timing Diagram. © 2010 Microchip Technology Inc. Min Typ Max -40 — +85 A -65 — +150 A — 89.3 — must not exceed the absolute maximum specification of +150°C. ...
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... DS22192C-page 8 1/DRCLK Timing Waveform for SDO t DOMDAT PRESCALE<1:0> 1/ 1/4 1/Prescale AMCLK MCLK Clock Divider Clock Divider t DRP DIS V IH 90% t HI-Z DIS 10% OSR<1:0> f ADC f ADC D S Output Sampling Data Rate Rate 1/OSR DMCLK DRCLK Clock Divider © 2010 Microchip Technology Inc. ...
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... OSR = 256 -60 16384 points Dithering OFF -80 -100 -120 -140 -160 -180 -200 0 500 1000 1500 Frequency (Hz) FIGURE 2-3: Spectral Response. © 2010 Microchip Technology Inc. = 5.0V 5.0V +25°C, MCLK = 4 MHz; PRESCALE = -0.5 dBFS @ 60 Hz -20 -40 -60 -80 -100 -120 -140 -160 -180 ...
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... OSR = 256 Dithering FIGURE 2-12: Distortion vs. Gain. Dithering ON Dithering OFF 32 64 128 256 Oversampling Ratio (OSR) Spurious Free Dynamic Dithering 128 256 Oversampling Ratio (OSR) Signal-to-Noise and OSR = 256 OSR = 128 OSR = 32 OSR = Gain (V/V) Signal-to-Noise and © 2010 Microchip Technology Inc. ...
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... -20 -40 -60 SINC filter notch at 15.625 Hz -80 10 100 1000 Input Signal Frequency (Hz) FIGURE 2-15: Total Harmonic Distortion vs. Input Signal Frequency. © 2010 Microchip Technology Inc. = 5.0V 5.0V +25°C, MCLK = 4 MHz; PRESCALE = -0.5 dBFS @ 60 Hz MCLK = 4 MHz 12 OSR = 256 Dithering On 10 ...
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... Match vs. Temperature. G=8 G=16 G=1 G=32 G=2 G 100 125 150 Temperature (ºC) Channel 0 Offset vs. G=8 G=1 G=16 G=32 G=2 G=4 - 100 125 150 Temperature (°C) Channel 1 Offset vs. Channel 0 Channel 1 - 100 125 150 Temperature (°C) Channel-to-Channel Offset © 2010 Microchip Technology Inc. ...
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... Negative Gain Error vs. Temperature 2.4 2.39 2.38 2.37 2.36 2.35 -50 - Temperature (°C) FIGURE 2-27: Internal Voltage Reference vs. Temperature. © 2010 Microchip Technology Inc. = 5.0V 5.0V +25°C, MCLK = 4 MHz; PRESCALE = -0.5 dBFS @ 60 Hz. IN 2.37165 2.3716 G=1 G=2 2.37155 G=8 2.3715 G=16 2.37145 G=4 2 ...
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... Input Voltage (V) FIGURE 2-32: Integral Nonlinearity (Dithering On). DS22192C-page 14 = 5.0V 5 25°C, MCLK = 4 MHz; PRESCALE = -0.5 dBFS @ 60 Hz. IN 2.5 2 1.5 1 0 FIGURE 2-33: Master Clock (MCLK). 0.5 AI BOOST OFF MCLK (MHz) Operating Current vs. © 2010 Microchip Technology Inc. ...
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... All the analog biases are enabled during a Reset so that the part is fully operational just after a RESET rising edge. This input is Schmitt triggered. © 2010 Microchip Technology Inc. Table 3-1. Function 3.2 Digital V ...
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... The DR pulse width is equal to one DMCLK period and the frequency of the pulses is equal to DRCLK (see Note: This pin should not be left floating when the DR_HIZN bit is low kΩ pull-up resistor connected to D © 2010 Microchip Technology Inc. Figure 1-3). is recommended. VDD ...
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... The maximum clock speed specified is 20 MHz when DV > 4.5V and 10 MHz otherwise. DD This input is Schmitt triggered. © 2010 Microchip Technology Inc. 3.14 SDO (Serial Data Output) This is the SPI data output pin. Data is clocked out of the device on the falling edge of SCK. ...
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... MCP3901 NOTES: DS22192C-page 18 © 2010 Microchip Technology Inc. ...
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... OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1 (see Figure 1-5). © 2010 Microchip Technology Inc. MCP3901 4.2 AMCLK – Analog Master Clock This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG1 PRESCALE< ...
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... The specification IN Section 2.0 “Typical Performance REF ). This REF Figure 2-24 and Figure 2-25. © 2010 Microchip Technology Inc. ...
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... SINAD log 10 + © 2010 Microchip Technology Inc. 4.11 Total Harmonic Distortion (THD) The total harmonic distortion is the ratio of the output harmonic’s power to the fundamental signal power for a sinewave input and is defined by EQUATION 4-7: ( THD dB The THD calculation includes the first 35 harmonics for the MCP3901 specifications ...
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... SINAD, THD, SFDR) are less signal dependent. The MCP3901 incorporates a proprietary dithering algorithm on both ADCs in order to remove Idle tones and improve THD, which is crucial for power metering applications. Figure 2-10 and © 2010 Microchip Technology Inc. ...
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... The PSRR specification can be DC (the power supply is taking multiple DC values (the power supply is a sinewave at a certain frequency with a certain common-mode). In AC, the amplitude of the sinewave is representing the change in the power supply. © 2010 Microchip Technology Inc defined as: EQUATION 4-11: PSRR dB Where V ...
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... Any SCK or MCLK edge coming while on this mode, will induce dynamic power consumption. Once any of the SHUTDOWN, CLKEXT and VREFEXT bits returns to ‘0’, the POR AV back to operation and AV DD monitoring block is DD monitoring can take place. DD © 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. 5.3 Delta-Sigma Modulator 5.3.1 ARCHITECTURE Both ADCs are identical in the MCP3901 and they include a second-order modulator with a multi-bit DAC architecture (see ADC composed of 4 comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum ...
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... This means that the first output of MDAT after Reset is always ‘0011’ after the first DMCLK rising edge. DELTA-SIGMA MODULATOR CODING Modulator MDAT Serial Output Code Stream +2 1111 +1 0111 0 0011 -1 0001 -2 0000 COMP COMP COMP <0> <1> <2> MDAT Serial Outputs in © 2010 Microchip Technology Inc. ...
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... OSR 1 z – Where: ⎛ ⎞ 2π exp --------------------- - ⎝ ⎠ DMCLK © 2010 Microchip Technology Inc. The Normal Mode Rejection Ratio (NMRR) or gain of the transfer function is given by the following equation: EQUATION 5-2: NMRR or: NMRR where Figure 5-3 shows the sinc filter frequency response: ...
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... Equation 5-1 5-2). (For 24-Bit Mode or WIDTH = 1) (For 16-Bit Mode or WIDTH = 0) Hexadecimal Decimal 0x7FFFFF + 8,388,607 0x7FFFFE + 8,388,606 0x000000 0 0xFFFFFF -1 0x800001 - 8,388,607 0x800000 - 8,388,608 Decimal Hexadecimal 23-Bit Resolution 0x7FFFFE + 4,194,303 0x7FFFFC + 4,194,302 0x000000 0 0xFFFFFE -1 0x800002 - 4,194,303 0x800000 - 4,194,304 © 2010 Microchip Technology Inc. ...
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... REFIN+/OUT and AGND. Decoupling at the sampling frequency, around 1 MHz, is important for any noise around this frequency will be aliased back into the conversion data (0.1 µF ceramic and 10 µF tantalum capacitors are recommended). © 2010 Microchip Technology Inc. Hexadecimal ...
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... Channel 0 and Channel 1 is equal to the phase delay setting. Note: A detailed explanation of the Data Ready pin (DR) with phase delay is present in Section 6.10 “Data Ready Latches and Data Ready Modes Phase Register Code = ------------------------------------------------- - DMCLK (DRMODE<1:0>)”. © 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. 5.11 Crystal Oscillator The MCP3901 includes a Pierce type crystal oscillator with very high stability and ensures very low tempera- ture and jitter for the clock generation. This oscillator can handle up to 16.384 MHz crystal frequencies pro- vided that proper load capacitances and the quartz quality factor are used ...
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... MCP3901 NOTES: DS22192C-page 32 © 2010 Microchip Technology Inc. ...
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... A<6:5>) so that multiple MCP3901 chips can be present on the same SPI bus with no data bus contention. This functionality enables three-phase power metering systems, containing three MCP3901 chips, controlled by a single SPI bus (single CS, SCK, SDI and SDO pins). © 2010 Microchip Technology Inc Device Address Bits FIGURE 6-1: The default device address bits are ‘ ...
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... MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI HI-Z SDO FIGURE 6-3: Device Write (SPI Mode 1,1 – Clock Idles High). DS22192C-page 34 R (ADDRESS) DATA (ADDRESS + 1) DATA A0 R (ADDRESS) DATA (ADDRESS + 1) DATA HI-Z HI HI-Z © 2010 Microchip Technology Inc. ...
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... Device Read (SPI Mode 0,0 – Clock Idles Low). CS Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI HI-Z SDO FIGURE 6-5: Device Write (SPI Mode 0,0 – Clock Idles Low). © 2010 Microchip Technology Inc. R (ADDRESS) DATA (ADDRESS + 1) DATA ...
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... CH1 ADC CH1 ADC CH1 ADC CH0 ADC CH0 ADC Upper byte Middle byte Lower byte Upper byte Middle byte CH0 ADC CH1 ADC CH1 ADC CH1 ADC Lower byte Upper byte Middle byte Lower byte © 2010 Microchip Technology Inc. ...
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... SDI 00011000 11XXXXXX CONFIG2 ADDR/W CONFIG2 Optional Reset of Both ADCs FIGURE 6-7: Recommended Configuration Sequence at Power-up. © 2010 Microchip Technology Inc. The following register sets are defined as types: TABLE 6-2: Type ADC DATA (both channels) CONFIGURATION 6.8 Situations that Reset ADC Data ...
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... DATA READY PIN (DR) CONTROL USING DRMODE BITS There are four modes that control the data ready pulses and these DRMODE<1:0> bits in the STATUS/COM register. For power metering applications, DRMODE<1:0> recommended (Default mode). modes are set with the © 2010 Microchip Technology Inc. ...
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... DR pin. The lagging ADC depends on the PHASE register and on the OSR. In this mode, the two ADCs are linked together so their data is latched together when the lagging ADC output is ready. © 2010 Microchip Technology Inc. MCP3901 6.10.2 DR PULSES WITH SHUTDOWN OR RESET CONDITIONS There will pulses if DRMODE< ...
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... MCP3901 PHASE < 0 FIGURE 6-8: Data Ready Behavior. DS22192C-page 40 PHASE = 0 PHASE > 0 © 2010 Microchip Technology Inc. ...
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... PHASE 0x07 GAIN 0x08 STATUS/ 0x09 COM CONFIG1 0x0A CONFIG2 0x0B © 2010 Microchip Technology Inc. read R Channel 0 ADC Data <23:0>, MSB First 24 R Channel 1 ADC Data <23:0>, MSB First 8 R/W Delta-Sigma Modulators Output Register 8 R/W Phase Delay Configuration Register ...
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... DATA_CHn <4> <3> <2> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 DATA_CHn DATA_CHn <17> <16> bit 16 R-0 R-0 DATA_CHn DATA_CHn <9> <8> bit 8 R-0 R-0 DATA_CHn DATA_CHn <1> <0> bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... COMPn_CH0: Comparator Outputs from Channel 0 Modulator bits Note 1: This register can be written in order to overwrite modulator output data, but any writing here will corrupt the ADC_DATA on the next three data ready pulses. © 2010 Microchip Technology Inc. This register should be used as a read-only register. (Note 1). ...
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... OSR = 32: The delay can go from -16 to +15. PHASE<4> is the sign bit. Phase<3> is the MSB and PHASE<0> the LSB. R/W-0 R/W-0 R/W-0 PHASE<4> PHASE<3> PHASE<2> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 PHASE<1> PHASE<0> bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... PGA_CH0<2:0>: PGA Setting for Channel 0 bits 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 BOOST_ BOOST_ PGA_CH0 CH1 CH0 < ...
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... DRMODE = 00 (linked ADCs), these data ready status bits will be updated synchro- nously upon the same event (lagging ADC is ready). These bits are also useful in systems where the DR pin is not used to save MCU I/O. © 2010 Microchip Technology Inc. for more output pin case the ...
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... ADC Channel 1 and Channel 0 data is not ready (default ADC Channel 1 data is not ready, ADC Channel 0 data is ready 01 = ADC Channel 0 data is not ready, ADC Channel 1 data is ready 00 = ADC Channel 1 and Channel 0 data is ready © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DRMODE<1> DRMODE<0> DRSTATUS_CH1 DRSTATUS_CH0 U = Unimplemented bit, read as ‘ ...
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... R/W-0 R/W-1 R/W-1 SHUTDOWN DITHER DITHER _CH0 _CH1 _CH0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared and external CLK. REF R/W-0 R/W-0 MODOUT MODOUT _CH1 _CH0 bit 8 R/W-0 R/W-0 VREFEXT CLKEXT bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... Internal voltage reference disabled, an external voltage reference must be placed between REFIN+/OUT and REFIN Internal voltage reference enabled (default) bit 0 CLKEXT: Clock Mode bit 1 = External Clock mode (internal oscillator disabled and bypassed – lower power mode – A crystal must be placed between OSC1/OSC2 (default) © 2010 Microchip Technology Inc. MCP3901 DS22192C-page 49 ...
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... MCP3901 NOTES: DS22192C-page 50 © 2010 Microchip Technology Inc. ...
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... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2010 Microchip Technology Inc. MCP3901 Example: MCP3901A0 e ...
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... MCP3901 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± 1RWH D N NOTE 1RWHV DS22192C-page 52 PP %RG\ >6623 © 2010 Microchip Technology Inc. φ L ...
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... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010 Microchip Technology Inc. MCP3901 DS22192C-page 53 ...
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... MCP3901 NOTES: DS22192C-page 54 © 2010 Microchip Technology Inc. ...
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... Corrected symbols inside the Functional Block Diagram figure. 2. Typographical revisions throughout document. Revision B (November 2009) The following is the list of modifications: 1. Removed the QFN package and all references to it. Revision A (September 2009) • Original Release of this Document. © 2010 Microchip Technology Inc. MCP3901 DS22192C-page 55 ...
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... MCP3901 NOTES: DS22192C-page 56 © 2010 Microchip Technology Inc. ...
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... Default option. Contact Microchip factory for other address options Tape and Reel Tape and Reel Temperature Range -40°C to +85°C Package Plastic Shrink Small Outline (SSOP), 20-lead © 2010 Microchip Technology Inc. X /XX Examples: a) Package Range MCP3901 . Two-Channel ΔΣ A/D ...
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... MCP3901 NOTES: DS22192C-page 58 © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 08/04/10 ...