AD73311AR Analog Devices Inc, AD73311AR Datasheet
AD73311AR
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AD73311AR Summary of contents
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AVDD1 VINP 0/38dB PGA VINN VOUTP CONTINUOUS +6/–15dB TIME PGA LOW-PASS FILTER VOUTN REFCAP REFERENCE REFOUT AGND1 Low Cost, Low Power CMOS General Purpose Analog Front End GENERAL DESCRIPTION The AD73311 is a complete front-end processor for general purpose ...
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AD73311–SPECIFICATIONS Parameter REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS 2, 3 Maximum Input Range at VIN Nominal Reference Level at VIN (0 dBm0) ...
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Parameter DAC SPECIFICATIONS (Continued) Power Supply Rejection 4, 5 Group Delay 2, 7 Output DC Offset 2, 8 Minimum Load Resistance Single-Ended Differential 2, 8 Maximum Load Capacitance Single-Ended Differential FREQUENCY RESPONSE 9 (ADC AND DAC) ...
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AD73311–SPECIFICATIONS Parameter REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS 2, 3 Maximum Input Range at VIN Nominal Reference Level at VIN (0 dBm0) ...
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Parameter DAC SPECIFICATIONS (Continued) Power Supply Rejection 4, 5 Group Delay 2, 7 Output DC Offset 2, 8 Minimum Load Resistance Single-Ended Differential 2, 8 Maximum Load Capacitance Single-Ended Differential FREQUENCY RESPONSE 9 (ADC AND DAC) ...
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AD73311 Table II. Current Summary (AVDD = DVDD = +5.5 V) Analog Internal Digital External Interface Conditions Current Current ADC On Only 8.5 6 ADC and DAC On 14.5 6 REFCAP On Only 0.8 0 REFCAP and REFOUT On Only ...
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TIMING CHARACTERISTICS Limit at Parameter T = – + Clock Signals 24 24.4 3 Serial Port 0.4 × 0.4 × ...
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AD73311 SE (I) THREE- STATE SCLK (O) SDIFS (I) SDI (I) THREE STATE SDOFS (O) THREE- STATE SDO ( –10 –85 –75 –65 –55 –45 –35 V – dBm0 ...
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... Although the AD73311 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model AD73311AR AD73311ARS EVAL-AD73311EB EVAL-AD73311EZ NOTES 0.3' Small Outline IC (SOIC Shrink Small Outline Package (SSOP). ...
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AD73311 Pin Number Mnemonic Function 1 VOUTP Analog Output from the Positive Terminal of the Output Channel. 2 VOUTN Analog Output from the Negative Terminal of the Output Channel. 3 AVDD1 Analog Power Supply Connection for the Output Driver. 4 ...
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TERMINOLOGY Absolute Gain Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at ...
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AD73311 FUNCTIONAL DESCRIPTION Encoder Channel The encoder channel consists of a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due to the high ...
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F = 4kHz B a. Analog Antialias Filter Transfer Function SIGNAL TRANSFER FUNCTION NOISE TRANSFER FUNCTION F = 4kHz B b. Analog Sigma-Delta Modulator Transfer Function F = 4kHz FS = DMCLK/256 B INTER c. Digital Decimator Transfer Function F ...
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AD73311 Analog Smoothing Filter & PGA The output of the single-bit DAC is sampled at DMCLK/8, therefore it is necessary to filter the output to reconstruct the low frequency signal. The decoder’s analog smoothing filter consists of a continuous-time filter ...
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MCLK (EXTERNAL) DIVIDER SE RESETB SDIFS SDI 8 CONTROL REGISTER A SPORT Register Maps There are two register banks for the AD73311: the control register bank and the data register bank. The control register bank consists of five read/write registers, ...
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AD73311 Address (Binary) Name 000 CRA 001 CRB 010 CRC 011 CRD 100 CRE 101 to 111 OPERATION Resetting the AD73311 The pin RESET resets all the control registers. All registers are reset to zero indicating that the default SCLK ...
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CONTROL REGISTER A 7 RESET Bit CONTROL REGISTER B 7 CEE Bit CONTROL REGISTER C 5VEN Bit ...
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AD73311 7 CONTROL REGISTER D MUTE Bit CONTROL REGISTER E 0 Bit Table XIV. Control Register D Description OGS2 ...
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Program (Control) Mode In Program Mode, CRA the user writes to the control registers to set up the device for desired operation—SPORT operation, cascade length, power management, input/output gain, etc. In this mode, the 16-bit information packet sent ...
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AD73311 SE SCLK SDOFS SDO SDIFS SDI DATA (CONTROL) WORD (DEVICE 1) SE SCLK SDOFS(2) SDO(2) SDOFS(1) SDIFS(2) SDO(1) SDI(2) SDIFS(1) SDI(1) DATA (CONTROL) WORD (DEVICE 2) SAMPLE WORD (DEVICE 1) SAMPLE WORD (DEVICE 2) SAMPLE WORD (DEVICE 1) DATA ...
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INTERFACING The AD73311 can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accompa- nying frame synchronization signal which is active high one ...
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AD73311 Control Register A contains a 3-bit field (DC0–2) that is pro- grammed by the DSP during the programming phase. The default condition is that the field contains 000b, which is equivalent to a single device in cascade (see Table ...
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In order to produce a direct sampling rate of 8 kHz necessary to reduce the external master clock to 8.192 MHz and to set the master clock divider to a ratio of 4, which results in a sample ...
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AD73311 It is also possible to subsample the DAC—update at a lower rate than the sampling rate—to reduce the overhead on the DSP. This, however, results in imaging of the subsampled bandwidth into the normal bandwidth, which implies that higher ...
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Figures 24 and 25 detail dc- and ac-coupled input circuits for single-ended operation respectively. 100 VINP V IN 0.047 F VINN REFOUT REFCAP 0.1 F CIN 100 VINP V IN 10k 0.047 F VINN REFOUT REFCAP 0.1 F Analog Output ...
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AD73311 Cascade Operation Where it is required to configure a cascade eight de- vices necessary to ensure that the timing of the SE and RESET signals is synchronized at each device in the cascade. A ...
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Good decoupling is important when using high speed devices. All analog and digital supplies should be decoupled to AGND and DGND respectively, with 0.1 µF ceramic capacitors in parallel with 10 µF tantalum capacitors. To achieve the best from these ...
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AD73311 APPENDIX A Programming a Single AD73311 for Data Mode Operation This section describes a typical sequence in programming a single codec to operate in normal DATA mode. It details the control (program) words that are sent to the device ...
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APPENDIX B Programming a Single AD73311 for Mixed Mode Operation This section describes a typical sequence in programming a single codec to operate in mixed mode. The device is connected in Nonframe Sync Loop-Back Mode (see Figure 14), which allows ...
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AD73311 APPENDIX C Configuring a Cascade of Two AD73311s to Operate in Data Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73311s to set them up for operation. It ...
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DSP TX REG CONTROL WORD 2 ADC WORD 001 001 00000011 0000 0000 0000 0000 STEP 1 DSP TX REG CONTROL WORD 1 CONTROL WORD 000 001 00000011 1 0 001 001 00000011 ...
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AD73311 APPENDIX D Configuring a Cascade of Two AD73311s to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73311s to configure them for operation in mixed ...
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DSP TX REG CONTROL WORD 2 ADC WORD 001 000 00010011 0000 0000 0000 0000 STEP 1 DSP TX REG CONTROL WORD 1 CONTROL WORD 000 000 00010011 1 0 001 000 00010011 ...
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AD73311 APPENDIX E DAC Timing Control Example The AD73311’s DAC is loaded from the DAC register contents just before the ADC register contents are loaded to the serial register (SDOFS going high). This default DAC load position can be advanced ...
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Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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AD73311 20-Lead Small Outline IC (R-20) 0.5118 (13.00) 0.4961 (12.60 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) 0.0118 (0.30) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) OUTLINE DIMENSIONS Dimensions ...