AD9878BST

Manufacturer Part NumberAD9878BST
DescriptionIC FRONT-END MIXED-SGNL 100-LQFP
ManufacturerAnalog Devices Inc
AD9878BST datasheets

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Specifications of AD9878BST

Rohs StatusRoHS non-compliantNumber Of Bits12
Number Of Channels4Power (watts)673mW
Voltage - Supply, Analog3.3VVoltage - Supply, Digital3.3V
Package / Case100-LQFP  
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AD9878
THEORY OF OPERATION
For a general understanding of the AD9878, refer to Figure 23, a
block diagram of the device architecture. The device consists of a
transmit path, receive path, and auxiliary functions, such as a PLL,
a ∑-∆ DAC, a serial control port, and a cable amplifier interface.
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a 12-bit
current output DAC.
The receive path contains a 10-bit ADC and dual 12-bit ADCs.
All internally required clocks and an output system clock are
generated by the PLL from a single crystal or clock input.
DATA
FIR LPF
ASSEMBLER
6
12
TxIQ[5:0]
I
4
12
TxSYNC
Q
4
f
(
)
IQCLK
MCLK
÷R
REFCLK
3
CA
CA PORT
INTERFACE
PROFILE
PROFILE
SELECT
4
SERIAL
SDIO
INTERFACE
5
IF10[4:0]
IF10
RxSYNC
Rx PORT
12
IF12[11:0]
IF12
AD9878
The 12-bit and 10-bit IF ADCs can convert direct IF inputs of
up to 70 MHz and run at sample rates of up to 29 MSPS. A video
input with an adjustable signal clamping level, along with the
10-bit ADC, allow the AD9878 to process an NTSC and a QAM
channel simultaneously.
The programmable ∑-∆ DAC can be used to control external
components, such as variable gain amplifiers (VGAs) or voltage-
controlled tuners. The CA port provides an interface to the
AD832x family of programmable gain amplifier (PGA) cable
drivers, enabling host processor control via the MxFE serial
port (SPORT).
QUADRATURE
MODULATOR
DAC GAIN CONTROL
CIC LPF
SINC
COS
BYPASS
12
4
12
4
SIN
DDS
÷4
÷4
f
(
)
MCLK
÷8
÷2
f
(
)
OSCIN
5
MUX
÷2
f
(
)
OSCIN
12
MUX
–
CLAMP LEVEL
Figure 23. AD9878 Block Diagram
Rev. A | Page 20 of 36
–1
12
MUX
DAC
–1
SINC
f
(
)
SYSCLK
f
(
)
OSCIN
PLL
OSCIN × M
FLAG0
8
Σ-∆ INPUT
Σ-∆
10
ADC
12
ADC
MUX
12
ADC
MUX
+
DAC
FSADJ
Tx OUTPUT
XTAL
OSCIN
Σ-∆ OUTPUT
FLAG[2:1]
IF10 INPUT
IF12B INPUT
VIDEO IN
IF12A INPUT

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